Abstract: Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.

Abstract: Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path. The controller is responsive to operating parameters to configure the adaptable data path to align a logical clock pulse on the signal received from the first clock domain with the same logical clock pulse in the second clock domain based on a measured delay between the first and second clock domains.

Abstract: Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: Parity and mask bit(s) are stored in a random access memory (RAM) that is coupled to a CAM. This CAM may be part of a TLB. The parity and mask bits(s) are stored in conjunction with the CAM entry write. Upon a CAM query match, the reference parity bit(s) and mask bit(s) stored at the address output by the CAM are output from the RAM. These reference parity bit(s) are compared to parity bit(s) generated from a query data value that is masked by the retrieved mask bit(s). In the absence of a CAM or RAM bit error, the reference parity bit(s) from the RAM and the parity bit(s) generated from the masked query data will match. If a CAM or RAM bit error occurred, these two sets of parity bit(s) will not match and thus an error will be detected. This error may be used as an indication that a false CAM match has occurred.

Abstract: A method of interstitial pre-discharge in a circuit includes providing the circuit, which includes a pre-charge node coupled to a clock evaluate node operable to receive a clock evaluate input cycle. Multiple pull-down stacks each including an interstitial node interconnect between the pre-charge node and ground. The interstitial node of each pull-down stack couples to an interstitial discharger device gated to ground. The method further includes operating the circuit in a pre-charge phase of the clock evaluate input cycle, including pre-charging the pre-charge node and the interstitial nodes, and keeping the devices in the pull-down stacks and the interstitial dischargers in a high impedance state. The method additionally includes operating the circuit in an evaluate phase of the clock cycle, including discharging the pre-charge node to ground through a pull-down stack, and discharging the interstitial node to ground through the interstitial discharger device to preclude charge share.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: Parity and mask bit(s) are stored in a random access memory (RAM) that is coupled to a CAM. This CAM may be part of a TLB. The parity and mask bits(s) are stored in conjunction with the CAM entry write. Upon a CAM query match, the reference parity bit(s) and mask bit(s) stored at the address output by the CAM are output from the RAM. These reference parity bit(s) are compared to parity bit(s) generated from a query data value that is masked by the retrieved mask bit(s). In the absence of a CAM or RAM bit error, the reference parity bit(s) from the RAM and the parity bit(s) generated from the masked query data will match. If a CAM or RAM bit error occurred, these two sets of parity bit(s) will not match and thus an error will be detected. This error may be used as an indication that a false CAM match has occurred.

Abstract: Parity bit(s) are stored in a random access memory (RAM) that is coupled to a CAM. This CAM may be part of a TLB. The parity bits(s) are stored in conjunction with the CAM entry write. Upon a CAM query match, the reference parity bit(s) stored at the address output by the CAM are output from the RAM. These reference parity bit(s) are compared to parity bit(s) generated from the query data value. In the absence of a CAM or RAM bit error, the reference parity bit(s) from the RAM and the parity bit(s) generated from the query data will match. If a CAM or RAM bit error occurred, these two sets of parity bit(s) will not match and thus an error will be detected. This error may be used as an indication that a false CAM match has occurred.