Abstract: A bipolar logic gate formed in an isolated N-type epitaxial layer in an integrated circuit device includes a normally operated vertical NPN switch transistor clamped by an inversely operated NPM clamp transistor. The base of the clamp transistor is formed by a high energy boron ion implant into a portion of the N-type epitaxial layer extending through the P-type base of the switch transistor. Multiple outputs are provided by Schottky barrier diodes formed on the N-type epitaxial layer.

Abstract: An input buffer gate for integrated injection logic (I.sup.2 L) circuits, including a multiple-collector transistor wherein a first collector is electrically common with the base thereof, a second (Schottky) collector is connected to receive an input signal, and a third collector which drives internal I.sup.2 L gates. The buffer has a high input breakdown voltage, virtually no input capacitance, power-up/power-down capability at logic "1" and virtually no input current at logic "0", very low storage time, and an input "1" threshold of about 0.5 volts.

Abstract: An integrated injection logic circuit, wherein the inverted, multi-collector transistor of each cell includes active base regions separated by dielectric isolation, and wherein a heavily-doped channel-stop layer is selectively located along the sidewalls of the isolation, to prevent collector-to-emitter surface inversion leakage. The isolated geometry substantially reduces parasitic capacitance between the substrate and the extrinsic base, thereby increasing the switching speed of the device.

Abstract: A TTL logic circuit employing single emitter PNP input transistors instead of a multi-emitter input stage, in order to reduce loading on input drive devices. The circuit features a logic swing of 1.6 volts centered on a circuit threshold of 1.6 volts with the logic 0 and logic 1 levels being internally clamped with p-n diode junctions to prevent transistor saturation and improve transistor switching speeds over those normally obtained using Schottky diode clamping techniques. The circuit output incorporates a Darlington stage and provides a logic 1 drive capability permitting the circuit to drive a terminated signal line having a low characteristic impedance, typically 50 ohms while maintaining a logic 1 level above 2.0 volts at 25.degree. C. Use of ion implantation techniques to define the isolation, emitter and base regions as well as the p-n diode junctions permits smaller device geometries and high F.sub.T transistors capable of high speed switching.