Patents by Inventor Benjamin J. Yurick

Benjamin J. Yurick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250067813
    Abstract: In some examples, the system includes a primary power domain having: a first ground; a first set of measurement devices coupled to the first ground and configured to be powered by at least one of a first set of power supplies; and a second set of measurement devices coupled to the first ground and configured to be powered by at least one of the first set of power supplies. In addition, the system includes at least two isolated secondary power domains coupled to the primary power domain, each having: a second ground different from the first ground; a transformer coupled to the primary power domain, to a second set of power supplies, and to the second ground; and a third set of measurement devices coupled to the second ground and configured to be powered by at least one of the second set of power supplies.
    Type: Application
    Filed: November 11, 2024
    Publication date: February 27, 2025
    Applicant: Keithley Instruments, LLC
    Inventors: Mark D. Zimmerman, Benjamin J. Yurick
  • Publication number: 20240348040
    Abstract: A test and measurement system includes one or more high voltage sources having a voltage high enough to be dangerous to users, an instrument backplane, having one or more backplane double fault protected interlocks, a power signal, and one or more slots configured to accept one or more modules, and one or more processors configured to execute code that causes the one or more processors to: monitor one or more signals from the one or more backplane double fault protected interlocks; and without engaging any of the one or more high voltage sources, determine an operational state and faulted condition of each of the one or more backplane double fault protected interlocks, and check wiring of an interlock pathway between the test and measurement instrument and a user system.
    Type: Application
    Filed: April 8, 2024
    Publication date: October 17, 2024
    Inventors: Benjamin J. Yurick, Mark D. Zimmerman
  • Publication number: 20230253887
    Abstract: A power supply block has multiple isolated power channels, the power supply comprising an interface magnetic component having multiple windings, each winding connected to a separate one of the isolated channels. A test and measurement instrument has a connector to allow the instrument to connect to a device under test, and a power supply block having multiple isolated power channels, the power supply block comprising an interface magnetic component having multiple windings, each winding connected to a separate one of the isolated power channels.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 10, 2023
    Applicant: Keithley Instruments, LLC
    Inventor: Benjamin J. Yurick
  • Patent number: 10514434
    Abstract: A mechanism is disclosed for mitigating common mode current in a test and measurement device. A measurement current can be received from a device under test via a measurement lead that couples a transformer in the test and measurement device with the device under test. The test and measurement device can then be calibrated to apply a nulling current to cancel the common mode current from the measurement current. Other embodiments can be described and/or claimed herein.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: December 24, 2019
    Assignee: KEITHLEY INSTRUMENTS, LLC
    Inventors: Benjamin J. Yurick, James A. Niemann
  • Publication number: 20180224515
    Abstract: A mechanism is disclosed for mitigating common mode current in a test and measurement device. A measurement current can be received from a device under test via a measurement lead that couples a transformer in the test and measurement device with the device under test. The test and measurement device can then be calibrated to apply a nulling current to cancel the common mode current from the measurement current. Other embodiments can be described and/or claimed herein.
    Type: Application
    Filed: February 6, 2017
    Publication date: August 9, 2018
    Inventors: Benjamin J. Yurick, James A. Niemann
  • Patent number: 9197236
    Abstract: A method for producing sampled data, which as the requested sampling period is increased, each sample is the average of an increasing number of ADC samples such that a maximum number of ADC samples are evenly space across the sample period. The method can include choosing one of multiple ADC with varying speed versus resolution capabilities to further increase the quality of the sampled data as the sampling period increases.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 24, 2015
    Assignee: TEKTRONIX, INC.
    Inventors: Wayne C. Goeke, Brian P. Frackelton, Benjamin J. Yurick