Patents by Inventor Benjamin JANN
Benjamin JANN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137051Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik
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Patent number: 11967980Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: GrantFiled: August 4, 2021Date of Patent: April 23, 2024Assignee: Intel CorporationInventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik
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Publication number: 20240072419Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: ApplicationFiled: November 8, 2023Publication date: February 29, 2024Applicant: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann
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Patent number: 11870132Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: GrantFiled: May 9, 2022Date of Patent: January 9, 2024Assignee: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann
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Publication number: 20230283311Abstract: A wireless communication device includes an antenna array with multiple antenna elements, an array of power amplifiers, and an array of phase shifters. Each antenna element is coupled to a power amplifier and a phase shifter. The device also includes transmitter circuitry coupled to the antenna array to encode a constant amplitude signal, which includes a power amplifier enable code to indicate which power amplifiers are to run in a subsequent data sample and a beam direction code to control beam direction of each phase shifter of the array of phase shifters in the subsequent data sample. The constant amplitude signal is then provided to the array of antenna elements and amplitude and phase modulation is combined over an air interface into a composite modulated signal.Type: ApplicationFiled: December 23, 2021Publication date: September 7, 2023Inventors: Benjamin Jann, Ashoke Ravi, Paolo Madoglio
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Publication number: 20230199516Abstract: A wireless communication device can include an antenna array and processing circuitry coupled to the antenna array to segment antenna elements of an antenna array into a configurable plurality of groups of antenna elements. The circuitry can also activate analog beamforming for at least one group of the plurality of groups of antenna elements. Subsequent to enabling analog beamforming, the processing circuitry can configure digital beamforming for the at !east one group based on a criterion.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Gregory Chance, Ashoke Ravi, Benjamin Jann, Paolo Madoglio
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Publication number: 20230189182Abstract: A wireless communication device can include an oscillator circuit. The oscillator circuit can include an oscillator and measurement circuitry coupled to the oscillator. The measurement circuitry can receive an output signal of the oscillator and measure oscillator error by comparing the output signal of the oscillator to a nominal frequency for an amount of time. The oscillator circuit can further include adjustment circuitry to adjust an oscillator frequency of the oscillator based on the measured oscillator error.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Inventors: Wayne Ballantyne, Benjamin Jann, Bruce Geren, Gregory Chance
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Publication number: 20230188178Abstract: A wireless communication device can include chains of circuitry, with at least one chain being a chain of transmitter circuitry to generate output radio frequency (RF) signals using baseband signals and at least one chain of receiver circuitry configured to receive RF signals. At least one chain can include a plurality of circuit blocks, a circuit block including at least one of oscillator circuitry, clocking circuitry, and phased lock loop (PLL) circuitry. The apparatus can include interconnect circuitry configured to couple one of the plurality of circuit blocks to a respective chain. Other systems, methods and apparatuses are described.Type: ApplicationFiled: December 13, 2021Publication date: June 15, 2023Inventors: Wayne Ballantyne, Benjamin Jann, Marco Bresciani, Wei Chen, Chien-Hwa Tou
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Publication number: 20220416770Abstract: A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Ali AZAM, Ashoke RAVI, Benjamin JANN
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Publication number: 20220407226Abstract: A phased array may include a clock stage configured to generate shifted clock signals. Each shifted clock signal may include a different phase. The phased array may also include a beamforming stage configured to generate a beamformed signal that includes a beam formed in a direction based on summed signals. In addition, the phased array may include slices. Each slice may include a filter stage and a feedback stage. The filter stage may be configured to generate a corresponding summed signal by filtering a portion of blocker and noise interference in a corresponding receive signal based on blocking signals and the shifted clock signals. The feedback stage may be configured to generate the blocking signals based on the shifted clock signals and the corresponding summed signal. The blocking signals may be representative of the blocker and noise interference in the corresponding receive signal.Type: ApplicationFiled: June 21, 2021Publication date: December 22, 2022Inventors: Benjamin JANN, Ashoke RAVI
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Publication number: 20220337292Abstract: A circuit for suppressing undesired sub-harmonics includes a plurality of mixers, wherein the plurality of mixers are connected in parallel; a plurality of local oscillator signals (LO), wherein each of the plurality of LOs is associated with one of the plurality of mixers; an input to receive a plurality of phases of a driving clock, wherein each of the plurality of phases is a sub-harmonic of the driving clock, and wherein each phase of the driving clock is distributed to one of the plurality of mixers; wherein the plurality of mixers are configured to suppress one or more of the plurality of phases of the driving clock and amplify a desired phase of the driving clock.Type: ApplicationFiled: December 27, 2019Publication date: October 20, 2022Inventors: Sanket JAIN, Benjamin JANN, Ashoke RAVI, Satwik PATNAIK
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Publication number: 20220278439Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: ApplicationFiled: May 9, 2022Publication date: September 1, 2022Applicant: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William J. Lambert, Benjamin Jann
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Patent number: 11380979Abstract: Disclosed herein are integrated circuit (IC) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). For example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (RFFE) die in electrical communication with the logic die; and an antenna patch, wherein the RFFE die is closer to the antenna patch than the logic die is to the antenna patch.Type: GrantFiled: March 29, 2018Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Sidharth Dalmia, Jonathan Jensen, Ozgur Inac, Trang Thai, William James Lambert, Benjamin Jann
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Patent number: 11374557Abstract: Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.Type: GrantFiled: December 28, 2018Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Benjamin Jann, Ashoke Ravi, Satwik Patnaik
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Publication number: 20220190851Abstract: An apparatus for transmitting output signals includes a pre-distortion circuit configured to perform digital pre-distortion (DPD) on input signal samples using a plurality of DPD coefficients to generate a plurality of pre-distorted samples. The apparatus further includes an estimation window search circuit configured to determine a signal power characteristic for each pre-distorted sample of the plurality of pre-distorted samples, and select a subset of the plurality of pre-distorted samples based on the determined signal power characteristics. The subset of the plurality of pre-distorted samples is selected to fit within a predetermined estimation window size. The plurality of DPD coefficients is updated based on the subset of the plurality of pre-distorted samples.Type: ApplicationFiled: December 15, 2020Publication date: June 16, 2022Inventors: Peter Pawliuk, Benjamin Jann, Gregory Chance
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Publication number: 20210391853Abstract: Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.Type: ApplicationFiled: December 28, 2018Publication date: December 16, 2021Inventors: Benjamin Jann, Ashoke Ravi, Satwik Patnaik, Elan Banin, Ofir Degani, Nebil Tanzi, Brandon Davis, Igal Kushnir, Jonathan Jensen, Sidharth Dalmia, Peter Pawliuk
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Publication number: 20210367629Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: ApplicationFiled: August 4, 2021Publication date: November 25, 2021Inventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Alexandros Margomenos, Igal Kushnir, Elan Banin, Ofir Degani
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Patent number: 11121731Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.Type: GrantFiled: August 26, 2019Date of Patent: September 14, 2021Assignee: Intel CorporationInventors: Ashoke Ravi, Benjamin Jann, Satwik Patnaik, Elan Banin, Igal Kushnir, Ofir Degani, Alexandros Margomenos
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Patent number: 10536118Abstract: A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.Type: GrantFiled: March 28, 2018Date of Patent: January 14, 2020Assignee: Intel IP CorporationInventor: Benjamin Jann
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Publication number: 20190305732Abstract: A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Inventor: Benjamin Jann