Abstract: Techniques are described herein for flushing volatile system memory to persistent memory after the loss of alternating current (AC) power. In some embodiments, the techniques include implementing an extended hold-up window long enough to complete a full flush of processor caches and memory controller buffers using energy available in the bulk capacitors of one or more power supplies after a power outage event. The voltage on the bulk capacitors within the one or more power supply units may be monitored, and a notification may be triggered when a programmable threshold voltage is detected on the bulk capacitors. The system may configure the voltage threshold to indicate that a certain minimum amount of energy used to successfully complete a cache flush operation is available. The techniques allow flushing volatile system caches without relying on battery backup units (BBUs), which may be cumbersome to install and maintain.

Abstract: Techniques are described herein processing asynchronous power transition events while maintaining a persistent memory state. In some embodiments, a system may proxy asynchronous reset events through system logic, which generates an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush prior to invoking a hardware power transition. Additionally or alternatively, the system may include a hardware backup mechanism to ensure all resets and power-transitions requested in hardware reliably complete within a bounded window of time independent of whether the persistent cache flush handler succeeds.

Abstract: Techniques described herein provide a handshake mechanism and protocol for notifying an operating system whether system hardware supports persistent cache flushing. System firmware may determine whether the hardware is capable of supporting a full flush of processor caches and volatile memory buffers in the event of a power outage or asynchronous reset. If the hardware is capable, then persistent cache flushing may be selectively enabled and advertised to the operating system. Once persistent cache flushing is enabled, the operating system and applications may treat data committed to volatile processor caches as persistent. If disabled or not supported by system hardware, then the platform may not advertise support for persistent cache flushing to the operating system.

Abstract: Techniques are described for identifying patterns of memory cells in a memory array that are predictive of non-correctable errors (“corruption patterns”). The techniques described herein identify patterns of cell errors that are likely to generate errors that cannot be corrected by an error correction code (ECC). The identification of non-correctable cells is accomplished by identifying a pattern of cell errors storing bit values that deviate from corresponding expected values. The pattern of these memory cells and various combinations of the cells in the pattern are compared to patterns of cells that are known to be correctable using ECC. If the error pattern or one or more of the combinations of erroneous cells in the pattern are not associated with patterns that are correctable via ECC, the error pattern is identified as predictive of a likely uncorrectable error.

Abstract: Techniques are described herein for flushing volatile system memory to persistent memory after the loss of alternating current (AC) power. In some embodiments, the techniques include implementing an extended hold-up window long enough to complete a full flush of processor caches and memory controller buffers using energy available in the bulk capacitors of one or more power supplies after a power outage event. The voltage on the bulk capacitors within the one or more power supply units may be monitored, and a notification may be triggered when a programmable threshold voltage is detected on the bulk capacitors. The system may configure the voltage threshold to indicate that a certain minimum amount of energy used to successfully complete a cache flush operation is available. The techniques allow flushing volatile system caches without relying on battery backup units (BBUs), which may be cumbersome to install and maintain.

Abstract: Techniques are described herein processing asynchronous power transition events while maintaining a persistent memory state. In some embodiments, a system may proxy asynchronous reset events through system logic, which generates an interrupt to invoke a special persistent flush interrupt handler that performs a persistent cache flush prior to invoking a hardware power transition. Additionally or alternatively, the system may include a hardware backup mechanism to ensure all resets and power-transitions requested in hardware reliably complete within a bounded window of time independent of whether the persistent cache flush handler succeeds.

Abstract: Techniques described herein provide a handshake mechanism and protocol for notifying an operating system whether system hardware supports persistent cache flushing. System firmware may determine whether the hardware is capable of supporting a full flush of processor caches and volatile memory buffers in the event of a power outage or asynchronous reset. If the hardware is capable, then persistent cache flushing may be selectively enabled and advertised to the operating system. Once persistent cache flushing is enabled, the operating system and applications may treat data committed to volatile processor caches as persistent. If disabled or not supported by system hardware, then the platform may not advertise support for persistent cache flushing to the operating system.

Abstract: Techniques are described for identifying patterns of memory cells in a memory array that are predictive of non-correctable errors (“corruption patterns”). The techniques described herein identify patterns of cell errors that are likely to generate errors that cannot be corrected by an error correction code (ECC). The identification of non-correctable cells is accomplished by identifying a pattern of cell errors storing bit values that deviate from corresponding expected values. The pattern of these memory cells and various combinations of the cells in the pattern are compared to patterns of cells that are known to be correctable using ECC. If the error pattern or one or more of the combinations of erroneous cells in the pattern are not associated with patterns that are correctable via ECC, the error pattern is identified as predictive of a likely uncorrectable error.