Patents by Inventor Benjamin John Orr

Benjamin John Orr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit devices with diodes integrated in subfins
    Patent number: 12720870
    Abstract: Integrated circuit (IC) devices with diodes formed in a subfin between a support structure of an IC device and one or more nanoribbon stacks are disclosed. To alleviate challenges of limited semiconductor cross-section provided by the subfin, etch depths in the subfin (i.e., depths of recesses in the subfin formed as a part of forming the diodes) are selectively optimized and varied. Deeper recesses are made in subfin portions at which diode terminals (e.g., anodes and cathodes) are formed, to increase the semiconductor cross-section in those portions, thus providing improved subfin contacts. Shallower recesses (or no recesses) are made in subfin portion between the diode terminals, to increase subfin retention. Thus, subfin diodes may be provided in a manner that enables improved diode conductance and/or improved current carrying capabilities while advantageously using substantially the same etch processes as those used for forming nanoribbon-based transistors elsewhere in the IC device.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: August 25, 2026
    Assignee: Intel Corporation
    Inventors: Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Benjamin John Orr, Chu-Hsin Liang, Biswajeet Guha, Saptarshi Mandal, Brian Greene, Sameer Jayanta Joglekar, Chung-Hsun Lin, Mauro J. Kobrinsky
  • INTEGRATED CIRCUIT DEVICES WITH DIODES INTEGRATED IN SUBFINS
    Publication number: 20230420443
    Abstract: Integrated circuit (IC) devices with diodes formed in a subfin between a support structure of an IC device and one or more nanoribbon stacks are disclosed. To alleviate challenges of limited semiconductor cross-section provided by the subfin, etch depths in the subfin (i.e., depths of recesses in the subfin formed as a part of forming the diodes) are selectively optimized and varied. Deeper recesses are made in subfin portions at which diode terminals (e.g., anodes and cathodes) are formed, to increase the semiconductor cross-section in those portions, thus providing improved subfin contacts. Shallower recesses (or no recesses) are made in subfin portion between the diode terminals, to increase subfin retention. Thus, subfin diodes may be provided in a manner that enables improved diode conductance and/or improved current carrying capabilities while advantageously using substantially the same etch processes as those used for forming nanoribbon-based transistors elsewhere in the IC device.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Benjamin John Orr, Chu-Hsin Liang, Biswajeet Guha, Saptarshi Mandal, Brian Greene, Sameer Jayanta Joglekar, Chung-Hsun Lin, Mauro J. Kobrinsky