Patents by Inventor Benjamin Koon Pan Chan
Benjamin Koon Pan Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971803Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical computer vision (CV) application are disclosed. A system includes a safety-critical CV application, a safety monitor, and a CV accelerator engine. The safety monitor receives an input image, test data, and a CV graph from the safety-critical CV application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and CV graph to the CV accelerator which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the CV accelerator engine and covers faults only observable at the level of the CV graph.Type: GrantFiled: December 10, 2021Date of Patent: April 30, 2024Assignee: ATI Technologies ULCInventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, Clarence Ip, Meghana Manjunatha
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Patent number: 11960410Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.Type: GrantFiled: November 25, 2020Date of Patent: April 16, 2024Assignee: ATI Technologies ULCInventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, William Lloyd Atkinson
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Patent number: 11954792Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.Type: GrantFiled: August 20, 2021Date of Patent: April 9, 2024Assignee: ATI Technologies ULCInventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Clarence Ip, Tung Chuen Kwong
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Patent number: 11816871Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first sub-frame portion by the first layer and continue the processing of the first sub-frame portion by the first layer when it is determined that there is sufficient image data available for the first layer to continue processing of the first sub-frame portion. Processing on a sub-frame portion basis continues for subsequent layers such that processing by a layer can begin as soon as sufficient data is available for the layer.Type: GrantFiled: December 30, 2020Date of Patent: November 14, 2023Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Tung Chuen Kwong, David Porpino Sobreira Marques, King Chiu Tam, Shilpa Rajagopalan, Benjamin Koon Pan Chan, Vickie Youmin Wu
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Publication number: 20230230367Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical inference application are disclosed. A system includes a safety-critical inference application, a safety monitor, and an inference accelerator engine. The safety monitor receives an input image, test data, and a neural network specification from the safety-critical inference application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and neural network specification to the inference accelerator engine which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the inference accelerator engine and covers faults only observable at the network level.Type: ApplicationFiled: March 17, 2023Publication date: July 20, 2023Inventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, David Porpino Sobreira Marques, Clarence Ip, Hung Wilson Yu
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Publication number: 20230110765Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.Type: ApplicationFiled: August 17, 2022Publication date: April 13, 2023Inventors: Benjamin Koon Pan CHAN, William Lloyd Atkinson, Tung Chuen Kwong, Guhan Krishnan
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Patent number: 11610142Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical inference application are disclosed. A system includes a safety-critical inference application, a safety monitor, and an inference accelerator engine. The safety monitor receives an input image, test data, and a neural network specification from the safety-critical inference application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and neural network specification to the inference accelerator engine which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the inference accelerator engine and covers faults only observable at the network level.Type: GrantFiled: May 28, 2019Date of Patent: March 21, 2023Assignee: ATI Technologies ULCInventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, David Porpino Sobreira Marques, Clarence Ip, Hung Wilson Yu
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Patent number: 11443051Abstract: A computer vision processor in an image cluster defines a fenced memory region (FMR) that controls access to image data stored in a first portion of a trusted memory region (TMR). The computer vision processor receives FMR requests from an application implemented in a processing cluster. The FMR requests are to access the image data in the first portion of the TMR. The computer vision processor selectively allows the requesting application to access the image data. In some cases, the computer vision processor acquires the image data and stores the image data in the first portion of the TMR, such as buffers in the TMR. A data fabric selectively permits the image processing application to access the data stored in the TMR based on whether the image cluster has opened or closed the FMR for the portion of the TMR.Type: GrantFiled: December 20, 2018Date of Patent: September 13, 2022Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULCInventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Tung Chuen Kwong, Guhan Krishnan
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Publication number: 20220207783Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first sub-frame portion by the first layer and continue the processing of the first sub-frame portion by the first layer when it is determined that there is sufficient image data available for the first layer to continue processing of the first sub-frame portion. Processing on a sub-frame portion basis continues for subsequent layers such that processing by a layer can begin as soon as sufficient data is available for the layer.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Tung Chuen Kwong, David Porpino Sobreira Marques, King Chiu Tam, Shilpa Rajagopalan, Benjamin Koon Pan Chan, Vickie Youmin Wu
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Publication number: 20220100634Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical computer vision (CV) application are disclosed. A system includes a safety-critical CV application, a safety monitor, and a CV accelerator engine. The safety monitor receives an input image, test data, and a CV graph from the safety-critical CV application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and CV graph to the CV accelerator which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the CV accelerator engine and covers faults only observable at the level of the CV graph.Type: ApplicationFiled: December 10, 2021Publication date: March 31, 2022Inventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, Clarence Ip, Meghana Manjunatha
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Patent number: 11210199Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical computer vision (CV) application are disclosed. A system includes a safety-critical CV application, a safety monitor, and a CV accelerator engine. The safety monitor receives an input image, test data, and a CV graph from the safety-critical CV application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and CV graph to the CV accelerator which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the CV accelerator engine and covers faults only observable at the level of the CV graph.Type: GrantFiled: May 31, 2019Date of Patent: December 28, 2021Assignee: ATI Technologies ULCInventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, Clarence Ip, Meghana Manjunatha
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Publication number: 20210383596Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.Type: ApplicationFiled: August 20, 2021Publication date: December 9, 2021Inventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Clarence Ip, Tung Chuen Kwong
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Patent number: 11100698Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.Type: GrantFiled: June 28, 2019Date of Patent: August 24, 2021Assignee: ATI Technologies ULCInventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Clarence Ip, Tung Chuen Kwong
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Publication number: 20210081328Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.Type: ApplicationFiled: November 25, 2020Publication date: March 18, 2021Inventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, William Lloyd Atkinson
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Publication number: 20200409773Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical graphics processing unit (GPU) compute application are disclosed. A system includes a safety-critical GPU compute application, a safety monitor, and a GPU. The safety monitor receives a compute grid, test vectors, and a compute kernel from the safety-critical GPU compute application. The safety monitor generates a modified compute grid by adding extra tiles to the original compute grid, with the extra tiles generated based on the test vectors. The safety monitor provides the modified compute grid and compute kernel to the GPU for processing. The safety monitor determines the likelihood of erroneous processing of the original compute grid by comparing the actual results for the extra tiles with known good results. The safety monitor complements the overall fault coverage of the GPU hardware and covers faults only observable at the application programming interface (API) level.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Tung Chuen Kwong, Clarence Ip, Benjamin Koon Pan Chan, Edward Lee Kim-Koon, Meghana Manjunatha
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Publication number: 20200410747Abstract: Systems, apparatuses, and methods for performing real-time video rendering with performance guaranteed power management are disclosed. A system includes at least a software driver, a power management unit, and a plurality of processing elements for performing rendering tasks. The system receives inputs which correspond to rendering tasks which need to be performed. The software driver monitors the inputs that are received and the number of rendering tasks to which they correspond. The software driver also monitors the amount of time remaining until the next video synchronization signal. The software driver determines which performance setting will minimize power consumption while still allowing enough time to finish the rendering tasks for the current frame before the next video synchronization signal. Then, the software driver causes the power management unit to provide this performance setting to the plurality of processing elements as they perform the rendering tasks for the current frame.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Benjamin Koon Pan Chan, William Lloyd Atkinson, Clarence Ip, Tung Chuen Kwong
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Publication number: 20200380383Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical inference application are disclosed. A system includes a safety-critical inference application, a safety monitor, and an inference accelerator engine. The safety monitor receives an input image, test data, and a neural network specification from the safety-critical inference application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and neural network specification to the inference accelerator engine which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the inference accelerator engine and covers faults only observable at the network level.Type: ApplicationFiled: May 28, 2019Publication date: December 3, 2020Inventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, David Porpino Sobreira Marques, Clarence Ip, Hung Wilson Yu
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Publication number: 20200379877Abstract: Systems, apparatuses, and methods for implementing a safety monitor framework for a safety-critical computer vision (CV) application are disclosed. A system includes a safety-critical CV application, a safety monitor, and a CV accelerator engine. The safety monitor receives an input image, test data, and a CV graph from the safety-critical CV application. The safety monitor generates a modified image by adding additional objects outside of the input image. The safety monitor provides the modified image and CV graph to the CV accelerator which processes the modified image and provides outputs to the safety monitor. The safety monitor determines the likelihood of erroneous processing of the original input image by comparing the outputs for the additional objects with a known good result. The safety monitor complements the overall fault coverage of the CV accelerator engine and covers faults only observable at the level of the CV graph.Type: ApplicationFiled: May 31, 2019Publication date: December 3, 2020Inventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, Clarence Ip, Meghana Manjunatha
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Patent number: 10853263Abstract: Systems, apparatuses, and methods for implementing a unified kernel virtual address space for heterogeneous computing are disclosed. A system includes at least a first subsystem running a first kernel, an input/output memory management unit (IOMMU), and a second subsystem running a second kernel. In order to share a memory buffer between the two subsystems, the first subsystem allocates a block of memory in part of the system memory controlled by the first subsystem. A first mapping is created from a first logical address of the kernel address space of the first subsystem to the block of memory. Then, the IOMMU creates a second mapping to map the physical address of that block of memory from a second logical address of the kernel address space of the second subsystem. These mappings allow the first and second subsystems to share buffer pointers which reference the block of memory.Type: GrantFiled: July 23, 2019Date of Patent: December 1, 2020Assignee: ATI Technologies ULCInventors: Tung Chuen Kwong, Benjamin Koon Pan Chan, William Lloyd Atkinson
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Patent number: 10824436Abstract: A hybrid co-processing system including both complex instruction set computer (CISC) architecture-based processing clusters and reduced instruction set computer (RISC) architecture-based processing clusters includes a parser to derive from a hardware configuration specific to the CISC architecture, such as an ACPI table, a device tree specific to the RISC architecture for booting. The hardware configuration information indicated by the device tree is specific to the RISC architecture, and in different cases includes more, less, or revised information than a corresponding ACPI table for the same hybrid co-processing system.Type: GrantFiled: December 13, 2018Date of Patent: November 3, 2020Assignee: ATI TECHNOLOGIES ULCInventors: Benjamin Koon Pan Chan, William Lloyd Atkinson