Patents by Inventor Benjamin L. Heilmann

Benjamin L. Heilmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12732174
    Abstract: A unified blender/eye-surf circuit has a first signal path operable in a blender mode to blend phases of two phase-shifted clock signals of a first plurality of phase-shifted clock signals in a fixed ratio to generate a first blended clock signal, and operable in an eye-surf test mode to create variable phase offsets as weighted combinations of pairs phase-shifted clock signals of the first plurality of phase-shifted clock signals to generate the first blended clock signal. A second signal path is operable in the blender mode to blend phases of two phase-shifted clock signals of a second plurality of phase-shifted clock signals in a fixed ratio to generate a second blended clock signal, and operable in an eye-surf test mode to create variable phase offsets as weighted combinations of pairs phase-shifted clock signals of the second plurality of phase-shifted clock signals to generate the second blended clock signal.
    Type: Grant
    Filed: November 27, 2024
    Date of Patent: September 8, 2026
    Assignee: Cadence Design Systems, Inc.
    Inventors: Satya Someswara Kaushik Yanamandra, Benjamin L. Heilmann, Mark A. Summers
  • Patent number: 12730150
    Abstract: Loopback testing of a phase interpolator (PI) in a serial link system. A CDR loop operates in a loopback mode until a sampling clock signal locks to a first valid lock point in a first UI. The CDR loop includes the PI and a phase blender for blending weights of multiple clock signals, phase offset from each other, to apply a blender delay to the sampling clock signal. The PI phase code is stored, and the sampled loopback signal is checked for bit errors. The blender delay is repeatedly adjusted to phase shift the sampling clock signal, locking the sampling clock signal with the CDR loop, and checking for bit errors of the loopback signal, such that the blender delay sweeps across at least one UI. For each further UI, the PI phase code is adjusted to target a further valid lock point, and the blender delay is swept.
    Type: Grant
    Filed: November 21, 2024
    Date of Patent: September 8, 2026
    Assignee: Cadence Design Systems, Inc.
    Inventors: Mark A. Summers, Benjamin L. Heilmann, Satya Someswara Kaushik Yanamandra
  • Patent number: 12658899
    Abstract: Phase interpolation techniques for clock and data recovery in high-speed serial interfaces. A phase interpolator interpolates between four input clock signals phase-offset by 90 degrees to generate eight output clock signals phase-offset by 45 degrees. The phase interpolator includes primary and secondary mixers that adjust phase values using a mixed thermometer-binary encoding scheme. The primary mixers use most-significant-bit (MSB) thermometer bits for coarse steps and least-significant-bit (LSB) thermometer and binary bits for fine half-steps. The secondary mixers additionally employ boundary bits to maintain proper phase relationships across quadrant transitions. The encoding scheme can reduce routing complexity while preserving monotonic phase progression over the full 360-degree range.
    Type: Grant
    Filed: January 13, 2025
    Date of Patent: June 16, 2026
    Assignee: Cadence Design Systems, Inc.
    Inventors: Satya Someswara Kaushik Yanamandra, Benjamin L. Heilmann, Douglas Scott Shelton