Abstract: The described invention provides a method of and circuitry for driving three or more groups of light emitting diodes (LEDs) using time division multiplexing, whereby a periodic signal is divided among groups of LEDs, each with a different color or color temperature. The LEDs may be driven to produce colors along a desired path of values. Other qualities of light besides color or color temperature may be similarly controlled along a path of values. In some implementations, the system may receive an oscillating signal, which may be used as a periodic signal for comparison with the control signal, and one or more offset voltages, each of which may be combined with the oscillating signal to provide a second oscillating signal. The control signal may be compared to both of the oscillating signals to determine if a particular LED group may be powered.

Abstract: A system allows a light fixture to have a wider range of color temperatures (CCT) while limiting the warmest temperature reached at full intensity. The CCT of the light output may be controlled independently of intensity across a certain range of CCT and dependent on intensity across another range. In an implementation, both intensity and CCT may be adjusted from a single handle, where the interface positions may be divided into multiple zones. In another implementation, intensity may be adjusted from a first handle, while CCT may be adjusted from a second handle. The CCT of the light output may be limited to cooler levels when the intensity is higher, and/or the intensity of the light may be limited to lower levels when the CCT is warmer.

Abstract: A method for high speed searching of a large database provides speed, throughput, and efficient memory usage comparable to TCAM-assisted searches without using dedicated processors. Successive groups of bits from a key are processed by tables in a search tree. The tables are constructed with different sizes and types according to the structure of the key and the distribution of information in the database. Each link to a subsequent table specifies both the type of the linked table and how many key bits the table will process. The tables include, but are need not be limited to, address offset tables that use bits from the key as an addressing offset to locate a result. Embodiments are implemented on pipeline processors that include internal memory units and access to external memory. Embodiments also include string compare tables, memory mapped tables, and/or instructions to continue searching on a different memory unit.

Abstract: A turbine shroud hanger apparatus for a gas turbine engine includes: an arcuate shroud hanger having at least one cooling hole passing therethrough, the cooling hole having an inlet and an outlet; and a filter carried by the shroud hanger positioned upstream of the inlet of the cooling hole, the filter having a plurality of openings formed therethrough which are sized to permit air flow through the cooling hole while preventing the entry of debris particles larger than a preselected size into the cooling hole.

Abstract: Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Abstract: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Abstract: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Abstract: Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Abstract: Polymerization of fluoroolefin monomers proceeds in a supercritical carbon dioxide solvent at high monomer loading levels to provide a high molecular weight polymer with low polydispersity and/or a unimodal molecular weight distribution.

Abstract: A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of error data occurring in one path and substituting therefor corresponding correct data from the other path to enable continuation of the data stream flow without interruption and without error.

Abstract: Polymerization of fluoroolefin monomers proceeds in a supercritical carbon dioxide solvent at high monomer loading levels to provide a high molecular weight polymer with low polydispersity and/or a unimodal molecular weight distribution.

Abstract: A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.

Abstract: A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of error data occurring in one path and substituting therefor corresponding correct data from the other path to enable continuation of the data stream flow without interruption and without error.

Abstract: A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.