Patents by Inventor Benjamin Neil Trombley
Benjamin Neil Trombley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104282Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Benjamin Neil Trombley, Chung-Lung K. Shum, Paul G. Villarrubia, K. Paul Muller, Michael Hemsley Wood, Daniel Arthur Gay, Hua Xiang, Karl Evan Smock Anderson, Erica Stuecheli, Michael Alexander Bowen, Randall J. Darden
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Patent number: 11916384Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.Type: GrantFiled: September 20, 2021Date of Patent: February 27, 2024Assignee: International Business Machines CorporationInventors: David Wolpert, Basanth Jagannathan, Michael Hemsley Wood, Leon Sigal, James Leland, Alexander Joel Suess, Benjamin Neil Trombley, Paul G. Villarrubia
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Publication number: 20230385503Abstract: Embodiments are provided for enhanced initial global placement in a circuit design in a computing system by a processor. A wire length minimization may be determined based on maximum population density constraints as a single player game theory for global placement of an integrated circuit.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexey Y LVOV, Gi-Joon NAM, Benjamin Neil TROMBLEY, Lakshmi N REDDY, Paul G VILLARRUBIA
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Publication number: 20230306179Abstract: Embodiments are provided for providing enhanced routing in a computing system by a processor. One or more of a plurality of short nets in a cell of an integrated circuit may be aligned for executing a routing operation, wherein a short net is a two-pin net having two gates on adjacent rows having a horizontal distance less than a selected threshold.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hua XIANG, Benjamin Neil TROMBLEY, Gi-Joon NAM, Gustavo Enrique TELLEZ, Paul G. VILLARRUBIA
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Publication number: 20230237233Abstract: Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.Type: ApplicationFiled: January 27, 2022Publication date: July 27, 2023Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hua XIANG, Benjamin Neil TROMBLEY, Gi-Joon NAM, Gustavo E. TELLEZ, Paul G. VILLARRUBIA
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Publication number: 20230090855Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: David Wolpert, Basanth Jagannathan, Michael Hemsley Wood, Leon Sigal, James Leland, Alexander Joel Suess, Benjamin Neil Trombley, Paul G. Villarrubia
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Patent number: 11288425Abstract: Carry out an initial wire-length-driven placement for an integrated circuit design embodied in an unplaced netlist, using a computerized placer, to obtain a data structure representing initial placements of logic gates. Identify at least one timing-critical source-sink path between at least one pair of source-sink endpoints in the data structure representing the initial placements. Create a new pseudo two-pin net for each pair of the at least one pair of source-sink endpoints to create an updated netlist. Carry out a revised wire-length-driven placement on the updated netlist to obtain a data structure representing revised placements.Type: GrantFiled: December 16, 2020Date of Patent: March 29, 2022Assignee: International Business Machines CorporationInventors: Benjamin Neil Trombley, Nathaniel Douglas Hieter, Daniel Arthur Gay
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Patent number: 10891411Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.Type: GrantFiled: November 29, 2018Date of Patent: January 12, 2021Assignee: International Business Machines CorporationInventors: Gi-Joon Nam, David John Geiger, Paul G. Villarrubia, Shyam Ramji, Myung-Chul Kim, Benjamin Neil Trombley
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Publication number: 20200175122Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Gi-Joon Nam, David John Geiger, Paul G. Villarrubia, Shyam Ramji, Myung-Chul Kim, Benjamin Neil Trombley
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Patent number: 10635773Abstract: The performance of a computer performing electronic design analysis is improved by representing a putative circuit design as a set of movable blocks of predetermined size which must fit into a bounding box (said blocks include a plurality of subsets to be interconnected by wires) and initially placing the set of blocks by quadratic initialization. Each of the blocks has first and second coordinates and weights are assigned to nets connecting those of the blocks within the subsets, the quadratic initialization in turn includes determining a cost of each of the nets connecting any two of the blocks within the subsets as one-half of a sum of squares of distances between the any two of the blocks; and minimizing a total cost over all of the nets to determine an initial placement of the set of blocks. Analytical placement is then carried out based on the initial quadratic placement.Type: GrantFiled: October 18, 2018Date of Patent: April 28, 2020Assignee: International Business Machines CorporationInventors: Myung-Chul Kim, Paul G. Villarrubia, Shyam Ramji, Gi-Joon Nam, Benjamin Neil Trombley
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Publication number: 20200125690Abstract: The performance of a computer performing electronic design analysis is improved by representing a putative circuit design as a set of movable blocks of predetermined size which must fit into a bounding box (said blocks include a plurality of subsets to be interconnected by wires) and initially placing the set of blocks by quadratic initialization. Each of the blocks has first and second coordinates and weights are assigned to nets connecting those of the blocks within the subsets, the quadratic initialization in turn includes determining a cost of each of the nets connecting any two of the blocks within the subsets as one-half of a sum of squares of distances between the any two of the blocks; and minimizing a total cost over all of the nets to determine an initial placement of the set of blocks. Analytical placement is then carried out based on the initial quadratic placement.Type: ApplicationFiled: October 18, 2018Publication date: April 23, 2020Inventors: Myung-Chul Kim, Paul G. Villarrubia, Shyam Ramji, Gi-Joon Nam, Benjamin Neil Trombley
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Publication number: 20200034507Abstract: A putative circuit design is represented as a set of movable blocks of predetermined size which must fit into a bounding box, with a plurality of subsets to be interconnected by wires. A total weighted wire length is determined as a function of coordinates of centers of the movable blocks by summing a half perimeter wire length over the plurality of subsets, and a density penalty is determined as a convolution of an indicator function of the current placement and a convolution kernel, via incremental integer computation without use of floating point arithmetic. Blocks are moved to minimize a penalty function which is the sum of the total weighted wire length and the product of a density penalty weight and the density penalty. The process repeats until a maximum value of the density penalty weight is reached or the density penalty approaches zero.Type: ApplicationFiled: July 27, 2018Publication date: January 30, 2020Inventors: Alexey Y. Lvov, Gi-Joon Nam, Benjamin Neil Trombley, Myung-Chul Kim, Paul G. Villarrubia
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Patent number: 10528695Abstract: A putative circuit design is represented as a set of movable blocks of predetermined size which must fit into a bounding box, with a plurality of subsets to be interconnected by wires. A total weighted wire length is determined as a function of coordinates of centers of the movable blocks by summing a half perimeter wire length over the plurality of subsets, and a density penalty is determined as a convolution of an indicator function of the current placement and a convolution kernel, via incremental integer computation without use of floating point arithmetic. Blocks are moved to minimize a penalty function which is the sum of the total weighted wire length and the product of a density penalty weight and the density penalty. The process repeats until a maximum value of the density penalty weight is reached or the density penalty approaches zero.Type: GrantFiled: July 27, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Alexey Y. Lvov, Gi-Joon Nam, Benjamin Neil Trombley, Myung-Chul Kim, Paul G. Villarrubia