Patents by Inventor Benjamin Orr
Benjamin Orr has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11996403Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.Type: GrantFiled: December 13, 2019Date of Patent: May 28, 2024Assignee: Intel CorporationInventors: Nidhi Nidhi, Rahul Ramaswamy, Walid M. Hafez, Hsu-Yu Chang, Ting Chang, Babak Fallahazad, Tanuj Trivedi, Jeong Dong Kim, Ayan Kar, Benjamin Orr
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Publication number: 20240170581Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.Type: ApplicationFiled: November 22, 2022Publication date: May 23, 2024Applicant: Intel CorporationInventors: Cheng-Ying Huang, Ayan Kar, Patrick Morrow, Charles C. Kuo, Nicholas A. Thomson, Benjamin Orr, Kalyan C. Kolluru, Marko Radosavljevic, Jack T. Kavalieros
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Publication number: 20240145471Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
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Publication number: 20240088133Abstract: An integrated circuit structure includes a sub-fin having a first type of dopant, a first diffusion region having the first type of dopant and in contact with the sub-fin, and a second diffusion region and a third diffusion region having a second type of dopant and in contact with the sub-fin. The first type of dopant is one of p-type or n-type dopant, and where the second type of dopant is the other of the p-type or n-type dopant. A first body of semiconductor material extends from the second diffusion region to the third diffusion region, and a second body of semiconductor material extends from the first diffusion region towards the second diffusion region. The first diffusion region is a tap diffusion region contacting the sub-fin. In an example, the first diffusion region facilitates formation of a diode for electrostatic discharge (ESD) protection of the integrated circuit structure.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Inventors: Nicholas A. Thomson, Ayan Kar, Kalyan C. Kolluru, Mauro J. Kobrinksy, Benjamin Orr
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Publication number: 20240088132Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Nicholas A. Thomson, Kalyan C. Kolluru, Ayan Kar, Chu-Hsin Liang, Benjamin Orr, Biswajeet Guha, Brian Greene, Chung-Hsun Lin, Sabih U. Omar, Sameer Jayanta Joglekar
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Publication number: 20240088136Abstract: An integrated circuit structure includes a sub-fin, a source region in contact with a first portion of the sub-fin, and a drain region in contact with a second portion of the sub-fin. A body including semiconductor material is above the sub-fin, where the body extends laterally between the source region and the drain region. A gate structure is on the body and includes (i) a gate electrode, and (ii) a gate dielectric between the gate electrode and the body. In an example, a first distance between the drain region and the gate electrode is at least two times a second distance between the source region and the gate electrode, where the first and second distances are measured in a same horizontal plane that runs in a direction parallel to the body. In an example, the body is a nanoribbon, a nanosheet, a nanowire, or a fin.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Ayan Kar, Nicholas A. Thomson, Kalyan C. Kolluru, Benjamin Orr
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Patent number: 11908856Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.Type: GrantFiled: December 18, 2019Date of Patent: February 20, 2024Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
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Publication number: 20240055497Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.Type: ApplicationFiled: October 24, 2023Publication date: February 15, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Tahir GHANI, Kalyan KOLLURU, Nathan JACK, Nicholas THOMSON, Ayan KAR, Benjamin ORR
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Publication number: 20240038889Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.Type: ApplicationFiled: October 12, 2023Publication date: February 1, 2024Inventors: Biswajeet GUHA, William HSU, Chung-Hsun LIN, Kinyip PHOA, Oleg GOLONZKA, Ayan KAR, Nicholas THOMSON, Benjamin ORR, Nathan JACK, Kalyan KOLLURU, Tahir GHANI
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Patent number: 11837641Abstract: Gate-all-around integrated circuit structures having adjacent deep via substrate contact for sub-fin electrical contact are described. For example, an integrated circuit structure includes a conductive via on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the conductive via. A gate stack is over the vertical arrangement of horizontal nanowires.Type: GrantFiled: December 18, 2019Date of Patent: December 5, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani, Kalyan Kolluru, Nathan Jack, Nicholas Thomson, Ayan Kar, Benjamin Orr
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Patent number: 11824116Abstract: Gate-all-around integrated circuit structures having devices with channel-to-substrate electrical contact are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A channel region of the first vertical arrangement of horizontal nanowires is electrically coupled to the first fin by a semiconductor material layer directly between the first vertical arrangement of horizontal nanowires and the first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A second vertical arrangement of horizontal nanowires is above a second fin. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires.Type: GrantFiled: December 18, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: Biswajeet Guha, William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Ayan Kar, Nicholas Thomson, Benjamin Orr, Nathan Jack, Kalyan Kolluru, Tahir Ghani
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Publication number: 20230089395Abstract: Integrated circuits including vertical diodes. In an example, a first transistor is above a second transistor. The first transistor includes a first semiconductor body extending laterally from a first source or drain region. The first source or drain region includes one of a p-type dopant or an n-type dopant. The second transistor includes a second semiconductor body extending laterally from a second source or drain region. The second source or drain region includes the other of the p-type dopant or the n-type dopant. The first source or drain region and second source or drain region are at least part of a diode structure, which may have a PN junction (e.g., first and second source/drain regions are merged) or a PIN junction (e.g., first and second source/drain regions are separated by an intrinsic semiconductor layer, or a dielectric layer and the first and second semiconductor bodies are part of the junction).Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: INTEL CORPORATIONInventors: Benjamin Orr, Nicholas A. Thomson, Ayan Kar, Nathan D. Jack, Kalyan C. Kolluru, Patrick Morrow, Cheng-Ying Huang, Charles C. Kuo
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Publication number: 20230088578Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction paths.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: INTEL CORPORATIONInventors: Nicholas A. Thomson, Ayan Kar, Benjamin Orr, Kalyan C. Kolluru, Nathan D. Jack, Patrick Morrow, Cheng-Ying Huang, Charles C. Kuo
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Publication number: 20230087444Abstract: Integrated circuits including lateral diodes. In an example, diodes are formed with laterally neighboring source and drain regions (diffusion regions) configured with different polarity epitaxial growths (e.g., p-type and n-type), to provide an anode and cathode of the diode. In some such cases, dopants may be used in the channel region to create or otherwise enhance a PN or PIN junction between the diffusion regions and the semiconductor material of a channel region. The channel region can be, for instance, one or more nanoribbons or other such semiconductor bodies that extend between the oppositely-doped diffusion regions. In some cases, nanoribbons making up the channel region are left unreleased, thereby preserving greater volume through which diode current can flow. Other features include skipped epitaxial regions, elongated gate structures, using isolation structures in place of gate structures, and/or sub-fin conduction paths that are supplemental or alternative to a channel-based conduction path.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Applicant: INTEL CORPORATIONInventors: Nicholas A. Thomson, Ayan Kar, Benjamin Orr, Kalyan C. Kolluru, Nathan D. Jack, Patrick Morrow, Cheng-Ying Huang, Charles C. Kuo
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Publication number: 20220415877Abstract: A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Benjamin Orr, Rohit Grover, Nathan Jack, Nicholas Thomson, Rui Ma, Ayan Kar, Kalyan Kolluru
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Publication number: 20220415925Abstract: Substrate-less lateral diode integrated circuit structures, and methods of fabricating substrate-less lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a fin or a stack of nanowires. A plurality of P-type epitaxial structures is over the fin or stack of nanowires. A plurality of N-type epitaxial structures is over the fin or stack of nanowires. One or more spacings are in locations over the fin or stack of nanowires, a corresponding one of the one or more spacings extending between neighboring ones of the plurality of P-type epitaxial structures and the plurality of N-type epitaxial structures.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Nicholas THOMSON, Kalyan KOLLURU, Ayan KAR, Rui MA, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Lin HU, Chung-Hsun LIN
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Publication number: 20220416022Abstract: Substrate-less nanowire-based lateral diode integrated circuit structures, and methods of fabricating substrate-less nanowire-based lateral diode integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a stack of nanowires. A plurality of P-type epitaxial structures is over the stack of nanowires. A plurality of N-type epitaxial structures is over the stack of nanowires. One or more gate structures is over the stack of nanowires. A semiconductor material is between and in contact with vertically adjacent ones of the stack of nanowires.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Nicholas THOMSON, Kalyan KOLLURU, Ayan KAR, Rui MA, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Lin HU, Chung-Hsun LIN, Sabih OMAR
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Publication number: 20220415881Abstract: Substrate-less silicon controlled rectifier (SCR) integrated circuit structures, and methods of fabricating substrate-less silicon controlled rectifier (SCR) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin portion and a second fin portion that meet at a junction. A plurality of gate structures is over the first fin portion and a second fin portion. A plurality of P-type epitaxial structures and N-type epitaxial structures is between corresponding adjacent ones of the plurality of gate structures. Pairs of the P-type epitaxial structures alternate with pairs of the N-type epitaxial structures.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Rui MA, Kalyan KOLLURU, Nicholas THOMSON, Ayan KAR, Benjamin ORR, Nathan JACK, Biswajeet GUHA, Brian GREENE, Chung-Hsun LIN
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Publication number: 20220415880Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Ayan KAR, Kalyan KOLLURU, Nicholas THOMSON, Rui MA, Benjamin ORR, Nathan JACK, Mauro KOBRINSKY, Patrick MORROW, Chung-Hsun LIN
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Publication number: 20220199609Abstract: Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Urusa ALAAN, Abhishek A. SHARMA, Charles C. KUO, Benjamin ORR, Nicholas THOMSON, Ayan KAR, Arnab SEN GUPTA, Kaan OGUZ, Brian S. DOYLE, Prashant MAJHI, Van H. LE, Elijah V. KARPOV