Abstract: A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design.

Abstract: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Abstract: A method, system and program for reducing or optimizing leakage power consumption in an integrated circuit produced in accordance with an integrated circuit model. A fast corner timing database and configurable timing constraints are used in conjunction with hold cell logic to identify a set of cells that should not be modified. A leakage optimization procedure is responsive to a slow corner timing database and timing constraints for a slow corner. The procedure is configurable and includes the repair of register transition violations. The procedure is performed on a select number of paths before an adjusted timing slack value is determined and cells are addressed in response to the number of failing timing paths associated with a cell. Some embodiments generate information in a router compatible format that identifies a desired modification to the top-level integrated circuit design.

Abstract: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.