Abstract: The invention is directed to a process for the continuous acetylation of wood elements. The process particularly combines a batchwise impregnation step, with a continuous reaction step. In order to realize this, a collection step is built-in, so as to allow batches of impregnated wood elements to be fed into a reactor in a continuous manner. Very high acetylation contents can be obtained, at a level that had not been achievable before in a continuous and non-catalyzed acetylation process.

Abstract: The invention is directed to a process for the continuous acetylation of wood elements. The process particularly combines a batchwise impregnation step, with a continuous reaction step. In order to realize this, a collection step is built-in, so as to allow batches of impregnated wood elements to be fed into a reactor in a continuous manner. Very high acetylation contents can be obtained, at a level that had not been achievable before in a continuous and non-catalyzed acetylation process.

Abstract: Disclosed is a modified refiner system for the acetylation of wood chip and/or wood fiber. The invention comprises a process for the acetylation of wood chip in a refiner system including a feed hopper component, a non-steam digester component and a refiner (defibrator) component in which the chip is contacted with an acetylating fluid between the hopper and the digester components within a connecting multi-zone compression feed screw.

Abstract: The invention is directed to a process for the continuous acetylation of wood elements. The process particularly combines a batchwise impregnation step, with a continuous reaction step. In order to realize this, a collection step is built-in, so as to allow batches of impregnated wood elements to be fed into a reactor in a continuous manner. Very high acetylation contents can be obtained, at a level that had not been achievable before in a continuous and non-catalyzed acetylation process.

Abstract: Disclosed is a modified refiner system for the acetylation of wood chip and/or wood fibre. The invention comprises a process for the acetylation of wood chip in a refiner system including a feed hopper component, a non-steam digester component and a refiner (defibrator) component in which the chip is contacted with an acetylating fluid between the hopper and the digester components within a connecting multi-zone compression feed screw.

Abstract: Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers.

Abstract: Mask design techniques for detection and removal of undesirable artifacts in SADP processes using multiple patterns are disclosed. Artifacts or spurs result from lithographic and chemical processing of semiconducting wafers. The spurs are undesirable because they can cause unwanted connections or act as electrical antennas. Spurs are detected using rule-based techniques and reduced by modifying lithographic masks. The severity of the detected spurs is determined, again using rule-based techniques. The effects of detected spurs can be reduced by modifying the decomposition of the drawn patterns into the two masks used for lithography. Mandrel masks are modified by add dummy mandrel material, and trim masks are modified by removing trim material. The resulting multi-pattern arrangement is used to fabricate the critical design elements that make up the semiconductor wafers.

Abstract: One embodiment of the invention provides a system that expedites or stabilizes convergence in a model-based optical proximity correction (OPC) process. During operation, the system receives a layout for an integrated circuit. Next, the system dissects shapes in the layout into a number of segments, and then runs a number of OPC iterations on the segments to produce an OPC-corrected layout. During each OPC iteration, the system calculates a chrome shift for each segment based on a current layout obtained from the previous iteration, wherein the chrome shift for a segment is measured from the previous position of the chrome edge in that segment. The system then calculates an adjusted chrome shift for each segment based on the newly calculated chrome shift and chrome shift values obtained in one or more previous iterations. Next, the system applies the adjusted chrome shift values to the current layout to obtain an updated layout.

Abstract: One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems due to a missing or an improperly placed assist feature. During operation, the system receives an uncorrected or corrected mask layout. The system then dissects the mask layout into segments. Next, the system identifies a problem area associated with a segment using a process-sensitivity model which can be represented by a multidimensional function that captures process-sensitivity information. Note that identifying the problem area allows a new assist feature to be added or an existing assist feature to be adjusted, thereby improving the wafer manufacturability. Moreover, using the process-sensitivity model reduces the computational time required to identify the problem area.

Abstract: One embodiment of the present invention provides a system that determines an assist feature placement. During operation, the system receives an initial assist feature placement for a layout. Next, the system determines assist feature perturbations using the initial assist feature placement. An assist feature perturbation typically comprises a few simple polygons. The system then determines perturbation values at evaluation points in the layout using the assist feature perturbations and an analytical model. If a process-sensitivity model is used, the perturbation value at an evaluation point is associated with the change in the through-process window at that point in the layout. Next, the system determines a change in the value of an objective function using the perturbation values. The objective function can be indicative of the overall manufacturability of the layout. The system then determines an assist feature placement using the change in the value of the objective function.

Abstract: One embodiment of the present invention provides a system that determines the locations and dimensions of one or more assist features in an uncorrected or corrected mask layout. During operation, the system receives a mask layout. The system then creates a set of candidate assist feature configurations, which specify locations and sizes for one or more assist features in the mask layout. Next, the system determines an improved assist feature configuration using the set of candidate assist feature configurations and a process-sensitivity model which can be represented by a multidimensional function that captures process-sensitivity information. Note that placing assist features in the mask layout based on the improved assist feature configuration improves the manufacturability of the mask layout. Moreover, using the process-sensitivity model to determine the improved assist feature configuration reduces the computational time required to determine the improved assist feature configuration in the mask layout.

Abstract: One embodiment of the present invention provides a system that identifies a problem edge in a mask layout which is likely to have manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process under nominal process conditions. The system also creates one or more off-target process models that model the semiconductor manufacturing process under one or more process conditions that are different from nominal process conditions. Next, the system computes a process-sensitivity model using the on-target process model and the off-target process models. The system then computes an edge-detecting process-sensitivity model by convolving the process-sensitivity model with an edge-detecting function which can be used to detect edges in an image. Next, the system identifies a problem edge in the mask layout using the edge-detecting process-sensitivity model.

Abstract: One embodiment of the invention provides a system that expedites or stabilizes convergence in a model-based optical proximity correction (OPC) process. During operation, the system receives a layout for an integrated circuit. Next, the system dissects shapes in the layout into a number of segments, and then runs a number of OPC iterations on the segments to produce an OPC-corrected layout. During each OPC iteration, the system calculates a chrome shift for each segment based on a current layout obtained from the previous iteration, wherein the chrome shift for a segment is measured from the previous position of the chrome edge in that segment. The system then calculates an adjusted chrome shift for each segment based on the newly calculated chrome shift and chrome shift values obtained in one or more previous iterations. Next, the system applies the adjusted chrome shift values to the current layout to obtain an updated layout.