Abstract: Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.

Abstract: Systems and methods for implementing count calibration for synchronous data transfer between clock domains are disclosed. An exemplary system may include a count calibration circuit for determining latency between an early clock domain and a late clock domain. The system may also include a data path configurable for synchronous data transfer between clock domains based at least in part on the latency.

Abstract: Systems and methods for implanting synchronous data transfer between clock domains are disclosed. An exemplary system may comprise an adaptable data path having an input for receiving a signal from a first clock domain and an output in a second clock domain. A controller is operatively associated with the adaptable data path.

Abstract: A voltage controller (150), the controller comprising: a voltage comparator (700) operative to provide a digital error signal (152); a compensator (300) operative to determine a digital control signal (154) based on said provided error signal; and a modulator (400) operative to provide a power control signal (156) based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: A method of interstitial pre-discharge in a circuit includes providing the circuit, which includes a pre-charge node coupled to a clock evaluate node operable to receive a clock evaluate input cycle. Multiple pull-down stacks each including an interstitial node interconnect between the pre-charge node and ground. The interstitial node of each pull-down stack couples to an interstitial discharger device gated to ground. The method further includes operating the circuit in a pre-charge phase of the clock evaluate input cycle, including pre-charging the pre-charge node and the interstitial nodes, and keeping the devices in the pull-down stacks and the interstitial dischargers in a high impedance state. The method additionally includes operating the circuit in an evaluate phase of the clock cycle, including discharging the pre-charge node to ground through a pull-down stack, and discharging the interstitial node to ground through the interstitial discharger device to preclude charge share.

Abstract: According to at least one embodiment, a system comprises means for performing an operation utilizing a clock signal. The system further comprises means for supplying a variable operating voltage to the performing means, and means for dynamically varying the frequency of the clock signal responsive to observed changes in the variable operating voltage.

Abstract: A method and system for evaluating the speed of a circuit are provided. In accordance with one embodiment, the method comprises determining during a first operational phase of a first operational cycle the propagation speed of a first signal in a first signal propagation path, and concurrently preventing all signals from propagating in a second signal propagation path substantially parallel with the first signal propagation path. The method further comprises determining during a second operational phase alternating with the first operational phase the propagation speed of a second signal in the second signal propagation path, and concurrently preventing all signals from propagating in the first signal propagation path.