Patents by Inventor Benjamin Pletcher

Benjamin Pletcher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230111571
    Abstract: Embodiments described herein are generally directed facilitating out-of-order execution of GPU texture sampler operations. An embodiment of a method includes a texture sampler of a GPU maintaining (i) a latency queue operable to store information regarding a set of transactions associated with each of multiple texture sampler operations and (ii) multiple virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time. Out-of-order processing of the texture sampler operations is facilitated by making use of the latency queue and the VC queues. For example, during a transaction processing interval, the availability of data in a cache for the transactions associated with each of the VC queues may be determined. A VC queue may be selected based on the determined availability of data. A transaction associated with a head of the selected VC queue may then be processed.
    Type: Application
    Filed: September 24, 2021
    Publication date: April 13, 2023
    Applicant: Intel Corporation
    Inventors: Carlos Nava Rodriguez, Benjamin Pletcher, Yoav Harel, Bret Martin, Sudarshanram Shetty
  • Publication number: 20230094696
    Abstract: Embodiments described herein are generally directed to a local cache structure within a shared function of a 3D pipeline that facilitates efficient caching of resource state. In an example, the cache structure is maintained within a sub-core of a GPU. The local cache structure includes (i) an SC having entries each containing a state of a binded resource, and (ii) a DSAT having entries each containing an index into the SC. The DSAT is tagged by SBTO values representing addresses of entries of a binding table. A request, including information indicative of an SBTO pointing to an entry within the binding table, is received for a state of a particular binded resource being accessed by a shared function of the 3D pipeline. Based on the SBTO and during a single access to the cache structure, a determination is made regarding whether the state of the particular binded resource is present.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Carlos Nava Rodriguez, Jonathan Hersh, Aditi Gautam, Yoav Harel, Benjamin Pletcher, Michael Apodaca
  • Patent number: 11281463
    Abstract: Methods and apparatus relating to conversion of an unsigned normalized (unorm) integer values to floating-point (float) values in low power are described. In an embodiment, conversion logic converts a unorm integer value to a floating-point value based on detection of whether the unorm integer matches one of three cases, wherein the unorm integer value comprises n bits. Memory stores a count value corresponding to n?1 bits of the unorm integer value after detection of a leading 1 in the unorm integer value. The three cases include: a first case with all zeros, a second case with all ones, and a third case with a combination of one or more zeros and one or more ones. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 25, 2018
    Date of Patent: March 22, 2022
    Assignee: INTEL CORPORATION
    Inventors: Benjamin Pletcher, Rahul Kumar
  • Publication number: 20190042246
    Abstract: Methods and apparatus relating to conversion of an unsigned normalized (unorm) integer values to floating-point (float) values in low power are described. In an embodiment, conversion logic converts a unorm integer value to a floating-point value based on detection of whether the unorm integer matches one of three cases, wherein the unorm integer value comprises n bits. Memory stores a count value corresponding to n?1 bits of the unorm integer value after detection of a leading 1 in the unorm integer value. The three cases include: a first case with all zeros, a second case with all ones, and a third case with a combination of one or more zeros and one or more ones. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 25, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Benjamin Pletcher, Rahul Kumar
  • Patent number: 9489707
    Abstract: Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Hema Chand Nalluri, Joy Chandra, Prosun Chatterjee, Benjamin Pletcher, Yoav Harel, Steven Spangler
  • Publication number: 20150091919
    Abstract: Embodiments described herein include a graphics processing unit. The graphics processing unit includes a plurality of execution units. The graphics processing unit also includes a plurality of sampler units. Each sampler unit corresponds to a sampler dispatch logic unit and at least one execution unit, and the sampler dispatch logic units are used to network the plurality of sampler units.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Hema Chand Nalluri, Joy Chandra, Prosun Chatterjee, Benjamin Pletcher, Yoav Harel, Steven Spangler
  • Publication number: 20070211068
    Abstract: Apparatus, systems and methods for implementing a reconfigurable floating point data filter are disclosed. For example, a method is disclosed, the method including configuring a texture filter in response to state data, where the state data specifying at least a data width of input texture data to be filtered, where the input texture data is in a floating point format, filtering the input texture data using the texture filter, and then reconfiguring the texture filter to be substantially fully utilized when the data width of the input texture data changes. Other implementations are also disclosed.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Inventors: Steven Spangler, Benjamin Pletcher