Abstract: The present invention relates to a method of testing of digital and analog circuits. If a fault is detected, after stimuli are applied and test measurements are made at some circuit nodes, steps are taken to locate faulty circuit components. At least one further node is selected for measurement on the basis of the levels of information that such nodes can provide. Further measurements aid fault location.For analog circuits, levels of information are determined by calculation of discrimination factors which depend on possible voltage ranges at unmeasured circuit nodes if various components are considered as faulty. The information gained from measurement at a further node is used to reduce the voltage ranges in order to aid selection of another node to measure.