Abstract: A memory system (3) for storing data messages communicated between a processor unit (13) and a communication module (11) comprises a memory array (4) having a plurality of memory buffers (B0-BM) for storing the data messages. First logic circuitry (28) generates a lock signal for a memory buffer which lock signal is valid when the processor trait (13) reads the first data word of the data message stored in the memory buffer whilst the memory buffer is not being accessed by the communication module (11). Module decode logic (22) coupled to receive the lock signal prevents the communication module (11) from writing a data message to a memory buffer when a valid lock signal has been generated for that memory buffer. The memory system (3) further comprises second logic circuitry (30) for providing a busy signal to the processor unit (13) when the processor unit reads the first data word from a memory buffer.

Abstract: A memory system (3) for storing data messages communicated between a processor unit (13) and a communication module (11), each data message comprising at least one data word, comprises a memory array (4) having a plurality of memory buffers (B0-BM), each buffer for storing a data message, and logic circuitry (24) coupled to the memory array (4). The logic circuitry (24) sets one bit of a data message stored in a memory buffer to a first logic state during a processor unit read access when the processor unit (13) reads a current data message from the memory buffer, and negates the one bit to a second logic state during a communication module write access when the communication module (11) writes a new data message into the memory buffer.