Abstract: An apparatus for enabling communication of information between processes being carried out on a computing system. Each process is assigned a control block including a specialized memory element. A process being executed modifies the state of each memory element if it discovers any information of interest to processes awaiting execution. Before the next process is executed, the memory element in its control block is tested to find out if the previously-executed process left any information of interest.

Abstract: A time accounting system for accounting for the time a process spends in a ready state, a wait state, or a running state. The system includes a time-of-day clock coupled to a central processing unit for outputting the time-of-day whenever a process changes state. A memory also coupled to the central processing unit stores the contents of a plurality of addressable process control blocks and each process control block includes first, second, and third storage locations for storing indications of the amount of time an associated process has been in the running, ready, and wait states, respectively. The central processor unit accesses the process control blocks and updates the process times stored therein in accordance with control signals generated by decoding a string of microinstructions stored in a control store memory. The time-of-day clock is accessed each time a process enters one of the running, ready, or wait states and each time the execution of a process is completed.

Abstract: A method of and apparatus for executing a family of instructions provides synchronization of processes in a multiprocessing system. Representations of processes awaiting data (information units) such as the completion of an asynchronous operation or the availability of a resource are stored in a memory in a first queue and representations of information units available to processes are stored in memory in a second queue. Transfer of information units between processes is controlled by data elements known as "semaphores" stored in the memory. Each semaphore contains a field having a numerical value identifying which of the two different kinds of queues is present.

Abstract: An information structure, or semaphore, serves as a signalling mechanism in process synchronization to connect a process and a non-simultaneously occurring event or resource. The semaphore is a data structure which stores representations of processes awaiting particular events or alternatively stores representations of events awaiting processes. Semaphore data structures are developed in two storage areas. First and second groups of process links are stored in the first storage area to establish, respectively, a first queue of processes ready to operate and a second queue, associated with the semaphore structure, of processes awaiting occurrences of a first particular event prior to being ready to operate. In the second storage area are stored first and second groups of message links to establish respectively a first queue, associated with a semaphore structure, representing second particular events and a second queue of unused links.

Abstract: Firmware is provided to change, upon execution, information in the system base which is located in both main memory and internal scratch pad registers.Hardware structures controlled by a microprogrammed control store, which provides for the generation of signals causing the creation of an image in main memory of a communication center comprised of registers at another location in the central processing unit. The microprogrammed control store further generates signals which causes the interchange of the information between the communication center and its image.

Abstract: Apparatus in a data processing system to initialize a semaphore held in a memory field of the data processing system or, alternatively, to restore the semaphore to a previous predetermined state. A count field, or tally field, provided in the semaphore is initialized by a particular instruction. The semaphore can be either a non-message semaphore or a message semaphore. The instruction initializes the semaphore count field of a non message semaphore to zero or a preloaded positive value. For a message semaphore, this instruction initializes the count field to zero. If the message semaphore previously had a positive count, the messages tied to the semaphore are released and the message links holding the messages are transferred to a free message link queue tied to the free link semaphore in the same semaphore descriptor segment.

Abstract: A procedure call mechanism implemented by hardware instructions and a hardware recognizable mechanism known as a stack. A procedure call is utilized by users who have written their programs in a modular way to pass from one program module to another, it is used by user programs to avail themselves of operating system services, and it is used by the operating system itself to achieve a responsive modular structure. The stack is a mechanism permitting the above to be done. A stack is a segment of memory and comprises a number of contiguous portions, known as stack-frames, which are accessed in last in, first out LIFO fashion. Each procedure call creates a stack frame, with subsequent procedure calls creating new stack frames; each exit deletes stack frames thus "popping up" a previous stack-frame. Thus a history of calls is correctly maintained in order to allow a return.

Abstract: Computer data and procedure protection by preventing processes from intering with each other or sharing each other's address space in an unauthorized manner is accomplished in hardware/firmware by restricting addressability to a segmented memory and by a ring protection mechanism.To protect information in segments shared by several processes from misuse by one of these processes a ring protection hardware system is utilized. There are four ring classes numbered 0 through 3. Each ring represents a level of system privilege with level 0 (the innermost ring) having the most privilege and level 3 (the outermost ring) the least. Every procedure in the system has a minimum and a maximum execute ring number assigned to it which specifies who may legally call the procedure. Also maximum write and read ring numbers specify the maximum ring numbers for which a write and/or read operation is permitted.

Abstract: One of a series of hardware/firmware instructions for converting a general purpose digital computer into a database machine by adding the capability of handling data base records. The invention comprises a hardware/firmware implemented machine instruction apparatus which fetches a record descriptor containing a referenced data base record type from main memory. The record type of the record to be checked, which is pointed to by a base register, is also fetched from main memory, and a comparison of the fetched record descriptor and type is made. A condition code is set to indicate the result of the comparison.

Abstract: A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an "ear" are as follows:A. when the process state switches from a running state to a waiting state; orB. when the process state switches from a running state to a suspended state.In both instances the CPU is given away and replaced by the PCB.

Abstract: A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows:1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU);2. ready -- the process is ready to run as soon as it is given control of the CPU;3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state;4. Suspended -- the process has been temporarily stopped (from a source external to the process).The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Abstract: One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction which determines the appropriate register where a database pointer is currently stored, retrieves the pointer from that register and then stores the pointer into main memory.

Abstract: Two of a series of hardware/firmware primitives are disclosed for converting a general purpose digital computer into a database machine. The invention comprises two hardware firmware implemented machine instructions which both fetch a set descriptor, which along with a base register BR, allow access to a record. For the Test Set Empty operation, the record accessed is an owner record and a check is made to see whether the set has any member records currently associated with it. For the Test Member Inserted operation, the record accessed is checked to see whether it is currently inserted as a member of a particular set (i.e., a part of that set).

Abstract: One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction called the find owner instruction, which fetches a set descriptor, which along with a base register BR, allows access to the owner pointer of a member record. The address of the owner record is then loaded into a register or registers.

Abstract: One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction which sequentially checks each database record in a database area beginning at the page/line number address (database address) contained in a register, until the next active record is located. The database address of that active record is then loaded into a register.