Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to come as close as possible to nulling the voltage magnitude at the output of the integrator. A controller keeps track of the charge that has been added to and removed from the integrator during the integrate cycle, and provides a coarse conversion value. The residual voltage is de-integrated to provide a fine conversion value, which is added to the coarse conversion value to provide a final value.

Abstract: An AC resistor attenuator with low parasitic capacitance coupling and, thus, a substantially constant attenuation value over a relatively wide frequency range is disclosed. The AC resistor attenuator comprises a first elongate resistor substantially entirely surrounded by a second elongate resistor. The first and second elongate resistors are thermally matched and have a substantially identical resistance profile. The first and second resistors are connected in series. The other ends of the first and second resistors are connected across the source of the signal to be attenuated. The attenuated signal is obtained at the junction between the first and second resistors. Except in the case where fifty percent (50%) attenuation is to be provided, the higher value resistance of the attenuator forms the first resistor and the lower value forms the second resistor.

Abstract: A signal whose RMS value is to be accurately determined is first converted into DC form by a relatively inaccurate RMS converter, such as a thermal RMS converter (15). The result is a first converter signal (Y.sub.1), which is stored for recirculation in a suitable storage device, such as a sample and hold circuit (17). Thereafter, the signal stored in the storage device is recirculated to the converter to create a second converter signal (Y.sub.2). Then, the second converter signal is subtracted from the doubled value of the first converter signal (2Y.sub.1 -Y.sub.2) to produce a corrected RMS signal (X). The difference between the first converter signal (Y.sub.1) and the corrected RMS signal (X) is then determined. This error signal (E) is stored. Next, a decision is made as to whether or not a fast mode of operation is to be followed. If it is not to be followed the corrected RMS signal is displayed.

Abstract: A sample and hold (S/H) circuit that produces an output signal having essentially zero offset voltage error is disclosed. The S/H circuit includes a pair of operational amplifiers (OA3 and OA4) that are connected in circuit during both the sample and the hold modes of operation. In the sample mode of operation one of the operational amplifiers (OA3) receives the incoming signal through a first resistor (R1) and in accordance therewith controls the magnitude of an inverted voltage stored on a storage capacitor (C1); and, the other operational amplifier (OA4) senses the stored inverted voltage and, in accordance therewith, applies a feedback voltage to the signal input of OA3 through a second resistor (R2). In the hold mode of operation OA4 senses the voltage stored on C1 and, in accordance therewith, via R2 and OA3 controls the output voltage, which has the correct polarity due to the inverted voltage being inverted by OA3.

Abstract: A signal whose RMS value is to be accurately determined is first converted into DC form by a relatively inaccurate RMS converter, such as a thermal RMS converter (15). The result is a first converter signal (Y.sub.1), which is stored for recirculation in a suitable device, such as a sample and hold circuit (17). The first converter signal is also doubled (2Y.sub.1) and stored (41). Thereafter the first converter signal stored in the storage device is recirculated to the converter to create a second converter signal (Y.sub.2). Then, the second converter signal is subtracted (43) from the doubled first converter (2Y.sub.1 -Y.sub.2) to produce a highly accurate RMS output signal.