Patents by Inventor BENJAMIN T. DUONG

BENJAMIN T. DUONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250216608
    Abstract: Technologies for micro-LED optical communication via glass waveguides are disclosed. In an illustrative embodiment, a glass interposer is mounted on a circuit board, and several integrated circuit (IC) dies are positioned above the glass interposer. A micro-LED assembly is mounted on each of the IC dies. Waveguides defined in the glass interposer can carry light between the micro-LED assemblies of the various IC dies, providing a high-bandwidth connection between the IC dies. The micro-LED assemblies can provide low-power, high-bandwidth connectivity between the IC dies and can operate in the high-temperature environment near the IC dies.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Benjamin T. Duong, Khaled Ahmed, Kristof Darmawikarta, Stephen Morein, Bai Nie
  • Publication number: 20250219032
    Abstract: Technologies for back side micro-LED assemblies are disclosed. In an illustrative embodiment, a micro-LED assembly includes several micro-LEDs and several photodiodes mounted on a base die. The base die is mounted on an integrated circuit (IC) die, such as a processor die. Through-silicon vias are defined in the IC die to carry electrical signals between the micro-LED assembly and transistors and other components near or at the front side of the IC die. An optical plug with an optical cable is positioned above the micro-LED assembly to couple light to and from the micro-LEDs and photodiodes. The short distance between the transistors on the front side of the IC die and the micro-LED assembly allows for high-bandwidth signals to be converted to optical signals with little loss. The optical cable can connect IC dies on the same circuit board, in the same housing, in the same rack, etc.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Benjamin T. Duong, Sandeep Gaan, Khaled Ahmed, Marcel M. Said, Stephen Morein
  • Publication number: 20250218915
    Abstract: An apparatus comprising a package substrate comprising a core layer; a pedestal embedded in the core layer; and a structure comprising a passive circuit component, wherein the structure is above the pedestal and is embedded in the core layer.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Tolga Acikalin, Soham Agarwal, Benjamin T. Duong, Jeremy D. Ecton, Kari E. Hernandez, Brandon Christian Marin, Pratyush Mishra, Pratyasha Mohapatra, Srinivas V. Pietambaram, Marcel M. Said, Gang Duan, Hiroki Tanaka, Robert A. May, Bai Nie, Sanjay Tharmarajah, Bohan Shan
  • Publication number: 20250219040
    Abstract: Technologies for components embedded in a substrate core are disclosed. In one embodiment, power components such as deep trench capacitors are disposed in a cavity defined in a substrate core for a circuit board of an integrated circuit package, such as a processor. The power components are stacked on top of each other, allowing for the stack of power components to match the height of the substrate core, even when the height of the individual power components is less than the height of the substrate core. Configuring the power components in this manner can provide mechanical stability to the power components and substrate core and provide power to a semiconductor die mounted on the circuit board.
    Type: Application
    Filed: December 28, 2023
    Publication date: July 3, 2025
    Inventors: Tolga ACIKALIN, Soham AGARWAL, Benjamin T. DUONG, Jeremy D. ECTON, Kari E. HERNANDEZ, Brandon Christian MARIN, Pratyush MISHRA, Pratyasha MOHAPATRA, Srinivas Venkata Ramanuja PIETAMBARAM, Marcel M. SAID, Suddhasattwa NAD, Gang DUAN, Zhixin XIE, Jung Kyu HAN, Mohamed R. SABER, Shuren QU, Naiya SOETAN-DODD, Teng SUN, Yuxin FANG
  • Publication number: 20250201787
    Abstract: Apparatus and methods for embedding deep trench capacitors (DTCs) in a package substrate. The method includes fabricating an integrated circuit on a silicon substrate core and identifying a deep trench capacitor (DTC) component to integrate with the integrated circuit. A cavity is created in the silicon substrate core to accommodate the DTC component. The cavity extends therethrough, like a through-hole. A temporary carrier is attached to the silicon substrate to create a cavity floor. A gap magnitude is determined, which is a difference between the thickness of the silicon substrate core and the thickness of the DTC component. An epoxy material with a minimum bond line that matches the gap magnitude is selected and implemented to fill the gap in fabrication. The minimum bond line is controlled by selection of particles to use in the epoxy material.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 19, 2025
    Applicant: Intel Corporation
    Inventors: Marcel M. Said, Tolga Acikalin, Soham Agarwal, Benjamin T. Duong, Jeremy D. Ecton, Kari E. Hernandez, Brandon Christian Marin, Pratyush Mishra, Pratyasha Mohapatra, Srinivas Venkata Ramanuja Pietambaram
  • Publication number: 20250201732
    Abstract: Various techniques for alleviating the negative effects of crack formation and propagation in glass, and related devices and methods, are disclosed. In one aspect, a microelectronic assembly includes a glass core having a structure of a crack-healing material on its edge, where the crack-healing material includes carbon, e.g., as a part of an organic monomer, oligomer, or a polymer, or as a part of a carbide of an inorganic material such as boron, titanium, or silicon. In another aspect, a microelectronic assembly includes a glass core in which particles that include an inorganic crack-healing material are dispersed, where the material includes carbon or boron, and a volume occupied by the particles is between about 5% and about 55% of the volume of the glass core. Formation of a crack in the glass core may activate the crack-healing material, causing it to at least partially fill the crack.
    Type: Application
    Filed: December 18, 2023
    Publication date: June 19, 2025
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Shuqi Lai, Khaled Ahmed, Srinivas Venkata Ramanuja Pietambaram, Benjamin T. Duong, Suddhasattwa Nad, Jeremy Ecton, Gang Duan, Sheng Li
  • Publication number: 20250192069
    Abstract: Various techniques for alleviating crack formation and propagation in glass, and related devices and methods, are disclosed. The techniques are based on providing various edge features before singulation of a glass panel into individual glass units. In one aspect, an edge feature may be an opening in an edge region of a glass core, the opening extending from one of the faces of the glass core towards the opposite face of the glass core and comprising a fill material such as an insulator material, a polymer, or a conductive material. In another aspect, an edge feature may be an anchor comprising a first pad over one of the faces of a glass core, a second pad over the opposite face of the glass core, and a pin, wherein the pin is attached to the first pad and extends from the first pad into the glass core.
    Type: Application
    Filed: December 12, 2023
    Publication date: June 12, 2025
    Inventors: Bohan Shan, Jesse C. Jones, Bai Nie, Whitney Bryks, Benjamin T. Duong, Pratyush Mishra, Jeremy Ecton, Yuqin Li, Pramod Malatkar, Yuvraj Singh, Yosef Kornbluth, Travis Palmer, Joshua Stacey, Mahdi Mohammadighaleni, Brandon C. Marin, Gang Duan, Suddhasattwa Nad, Srinivas Venkata Ramanuja Pietambaram, Pratyasha Mohapatra, Soham Agarwal, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Hongxia Feng, Haobo Chen, Hiroki Tanaka, Aaron Michael Garelick, Sairam Agraharam, Rahul N. Manepalli, Bin Mu, Jose Waimin, Ryan Carrazzone, Dingying Xu, Xiaoying Guo, Xiao Liu, Xiyu Hu, Yi Cao
  • Publication number: 20250110289
    Abstract: A ferrule of an optical connector device is to accept one or more optical fibers in one or more fiber holes of the ferrule, the ferrule is formed from a dielectric material. The ferrule includes a face to interface with an optical socket of another device, where ends of the one or more optical fibers are exposed at the face to communicate photon signals with another device. The ferrule further includes alignment features formed in the dielectric layer to align the ends of the one or more optical fibers with one or more waveguides of the other device.
    Type: Application
    Filed: September 30, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Benjamin T. Duong, Gang Duan, Sandeep Gaan, Donald Hammon, Wesley B. Morgan
  • Publication number: 20250112175
    Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
  • Publication number: 20250105222
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways through the RDL, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the RDL and by interconnects.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Gang Duan, Yosuke Kanaoka, Minglu Liu, Srinivas V. Pietambaram, Brandon C. Marin, Bohan Shan, Haobo Chen, Benjamin T. Duong, Jeremy Ecton, Suddhasattwa Nad
  • Publication number: 20250105209
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: Intel Corporation
    Inventors: Gang Duan, Yosuke Kanaoka, Minglu Liu, Srinivas V. Pietambaram, Brandon C. Marin, Bohan Shan, Haobo Chen, Jeremy Ecton, Benjamin T. Duong, Suddhasattwa Nad
  • Publication number: 20250096053
    Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Brandon C. Marin, Bohan Shan, Tarek A. Ibrahim, Srinivas V. Pietambaram, Gang Duan, Benjamin T. Duong, Suddhasattwa Nad
  • Patent number: 12249584
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: March 11, 2025
    Assignee: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Benjamin T. Duong, Srinivas V. Pietambaram, Tarek A. Ibrahim
  • Publication number: 20240219632
    Abstract: Technologies for integrated graded index (GRIN) lenses for photonic circuits is disclosed. In one illustrative embodiment, a glass substrate has a cavity in which a GRIN lens is disposed. In other embodiments, the GRIN lens may be on a surface of the glass substrate. The GRIN lens focuses and collimates light to a free-space beam from a waveguide defined in the glass substrate. Another component such as a photonic integrated circuit (PIC) die may also have a GRIN lens and focus the free-space beam into a waveguide in the PIC die. The use of GRIN lenses allows for passive coupling to waveguides without further active alignment that minimizes signal transmission losses.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Umesh Prasad, Suddhasattwa Nad, Benjamin T. Duong, Yi Yang
  • Publication number: 20240222295
    Abstract: Embodiments described herein enable a microelectronic assembly that includes: a package substrate having a core including a solid continuous glass material with one or more capacitors in the solid continuous glass material and integrated circuit (IC) dies coupled to the package substrate. The structure of each capacitor includes a dielectric structure between two conductive structures. The dielectric structure comprises a layer of organic dielectric material between two layers of crystalline inorganic material. The crystalline inorganic material is in direct contact with one of the two conductive structures.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: Mahdi Mohammadighaleni, Joshua Stacey, Benjamin T. Duong, Thomas S. Heaton, Dilan Seneviratne, Rahul N. Manepalli
  • Publication number: 20240178146
    Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a glass core having a surface, a first region having a first concentration of ions extending from the surface of the core to a first depth; a second region having a second concentration of ions greater than the first concentration of ions, the second region between the first region and the surface of the core; a dielectric with a conductive pathway at the surface of the glass core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Applicant: Intel Corporation
    Inventors: Benjamin T. Duong, Whitney Bryks, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Ravindranath Vithal Mahajan
  • Publication number: 20240178084
    Abstract: Disclosed herein are microelectronic assemblies including strengthened glass cores, as well as related devices and methods. In some embodiments, a microelectronic assembly may include a core made of glass and having a surface, the core further including a first region having a first concentration of ions and a second region having a second concentration of ions at the surface of the core; and a third region having a third concentration of ions, wherein the second region is between the third region and the surface of the core, and wherein the third concentration of ions is less than the first and second concentrations of ions; a dielectric with a conductive pathway at the surface of the core; and a die electrically coupled to the conductive pathway in the dielectric at the surface of the core by an interconnect.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Applicant: Intel Corporation
    Inventors: Soham Agarwal, Benjamin T. Duong
  • Patent number: 11948898
    Abstract: Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kristof Darmawikarta, Srinivas V. Pietambaram, Hongxia Feng, Xiaoying Guo, Benjamin T. Duong
  • Publication number: 20240079339
    Abstract: Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Benjamin T. Duong, Suddhasattwa Nad, Jeremy Ecton
  • Publication number: 20230420373
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate having a cavity; a first die at least partially nested in the cavity in the first layer of the substrate, the first die having a surface with conductive contacts; a liner layer on the first layer, in a portion of the cavity, and on and around the first die, wherein a material of the liner layer includes: silicon or aluminum, and one or more of nitrogen, oxygen, and carbon; a second layer on the liner layer, wherein the second layer extends into the cavity and is on and around the first die; and a second die on the second layer, wherein the second die is electrically coupled to the conductive contacts on the first die by conductive vias through the second layer and the liner layer.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Benjamin T. Duong, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram