Abstract: A data processing system has a host processor, a RAM, a cache memory for storing segments of data, a plurality of disk drive devices and a storage control unit for controlling data transfers, data from the host processor being written to the cache memory and subsequently destaged to the disks. The storage control unit continuously updates a variable indicating the number of written-to segments resident in the cache memory that have not been destaged to the disks. The variable is stored in the RAM. A File Status flipflop is responsive to the variable to produce a "good file" signal when the variable is zero. The File Status flipflop is provided with an auxiliary power supply to maintain it in its present state in the event all power to the cache memory is terminated.

Abstract: A system including a host processor, a disk drive device and a cache store for storing segments of data most recently used or most likely to be used, is provided with a separate store for storing a segment descriptor table. The table has an entry therein corresponding to each segment in the cache store and an entry in the table is formed or reformed each time data is written into its corresponding segment in the cache store. A copy of the segment descriptor table entry thus formed is stored in the cache store at the end of its corresponding data segment. The segment descriptor table entries are normally utilized to manage their corresponding segments. If the store for the table should fail, the copies of the segment descriptor table entries in the cache store may be utilized to control the transfer of data segments in the cache store to their proper locations in disk storage.

Abstract: In a system wherein processors are connected through channel units to disk devices, two storage control units (SCU's) are provided between the channel units and the disk devices. The SCU's receive commands from the processor and issue seek instructions to the devices to locate the disk space specified by the commands, provided that a copy of the data from the specified disk space is not resident in a cache store. The commands may be queued for a time in a memory which is accessible by both SCU's. Before issuing a seek instruction to a device, an SCU first determines whether it is the only SCU having a path through a channel unit back to the processor which issued the command or whether there is a path from each SCU to the processor. If both SCU's have a path back to the processor, the SCU issues an untagged seek instruction to the device. If not, the SCU issues a tagged seek instruction to the device.