Abstract: The subject disclosure describes a structure and method that generates the average of two or more reference quantities (e.g., reference voltage potentials) and monitors the integrity of the voltage reference potentials. The subject technology produces a reference with improved accuracy and more accurate monitoring compared to traditional techniques. For example, the subject technology provides for a fault circuit that includes a monitoring circuit, and an averaging circuit configured to receive a plurality of reference signals and to produce an averaged reference signal based on the received plurality of reference signals. In some examples, the monitoring circuit is configured to receive the averaged reference signal from the averaging circuit, compare the averaged reference signal to each of the plurality of reference signals, and generate a fault signal when the averaged reference signal deviates from at least one of the plurality of reference signals by at least a threshold value.

Abstract: The subject disclosure describes a structure and method that generates the average of two or more reference quantities (e.g., reference voltage potentials) and monitors the integrity of the voltage reference potentials. The subject technology produces a reference with improved accuracy and more accurate monitoring compared to traditional techniques. For example, the subject technology provides for a fault circuit that includes a monitoring circuit, and an averaging circuit configured to receive a plurality of reference signals and to produce an averaged reference signal based on the received plurality of reference signals. In some examples, the monitoring circuit is configured to receive the averaged reference signal from the averaging circuit, compare the averaged reference signal to each of the plurality of reference signals, and generate a fault signal when the averaged reference signal deviates from at least one of the plurality of reference signals by at least a threshold value.

Abstract: A calibration circuit for synchronizing a switching regulator includes a phase locked loop circuit to generate one or more control signals based on an output of the switching regulator. A digital calibration circuit provides a digital output signal based on the control signals from the phase locked loop circuit. A timer can provide switching pulses to the switching regulator based on the digital output signal and the control signals. The phase locked loop circuit can adjust the control signals based on a reference clock signal to synchronize a feedback signal of the switching regulator with the reference clock signal.

Abstract: An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.

Abstract: An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.

Abstract: A digital to analog converter (DAC) system includes a resistor network providing enhanced response time and steady state characteristics.