Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including an absorber layer separated from an optical grating coupler by a cladding material. The absorber is positioned to receive light reoriented through the optical grating coupler.

Abstract: Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including an absorber layer separated from an optical grating coupler by a cladding material. The absorber is positioned to receive light reoriented through the optical grating coupler.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including an optical medium for light signals; and an optical grating coupler coupled to the optical medium. The optical grating coupler is configured to reorient light from the optical medium. A cladding material is over the optical grating coupler. An absorber layer is over the cladding material, and vertically above the optical grating coupler.

Abstract: Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.

Abstract: Disclosed are embodiments of a microelectronics package that includes: first and second substrates (each having first and second sides); a chip; and a multi-element antenna connected to the chip. The chip is mounted on the first side of the first substrate. A first antenna element of the antenna is on the second side of the first substrate and electrically connected to the chip. The first side of the second substrate is adhered to the second side of the first substrate (i.e., covering the first antenna element). A second antenna element of the antenna is on the second side of the second substrate overlaying the first antenna element and physically separated therefrom by at least one ultra-low-K dielectric region within the first side of the second substrate and/or the second side of the first substrate. Optionally, the package includes multiple chips and/or multiple antennas. Also disclosed are associated method embodiments.

Abstract: Photonic integrated circuit (PIC) packages include a PIC die. The PIC die includes a waveguide(s) positioned on the PIC die, and a groove(s) formed in a surface of the PIC die. The groove(s) corresponds to and is positioned directly adjacent the waveguide(s). The PIC package also includes an optical fiber(s) operatively coupled to the waveguide(s) of the PIC die. The optical fiber(s) are positioned in the groove(s) of the PIC die and include an end positioned adjacent the waveguide(s). Additionally, the PIC package includes a plate positioned over a section of the optical fiber(s), and the plate includes a first edge positioned adjacent the waveguide(s) of the PIC die, and a second edge positioned opposite the first edge. The PIC package also includes a first adhesive disposed along the second edge of the plate and a second adhesive disposed along the first edge of the plate.

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

Abstract: A photonic integrated circuit (PIC) fan-out package and related methods of forming same are disclosed. The PIC fan-out package includes: an overmold body; a PIC die in the overmold body, the PIC die including electro-optic circuitry; a plurality of optical fiber stubs operatively coupled to the electro-optic circuitry; an edge fiber coupling interface in a lateral side of the overmold body for coupling the plurality of optical fiber stubs to external optical fibers using a connector; an ancillary device in the overmold body; a redistribution wiring layer (RDL) interposer adjacent the overmold body and electrically connected to the PIC die and the ancillary device; and a ball grid array (BGA) electrically coupled to the PIC die and the ancillary device by the RDL interposer, the BGA configured to electrically couple the PIC die and the ancillary device to a printed circuit board (PCB).

Abstract: A photonic integrated circuit (PIC) package includes a PIC die including electro-optical circuitry having an optical waveguide system therein and a V-groove fiber optic receptacle on a first surface thereof. The V-groove fiber optic receptacle positions an optical element, e.g., optical fiber(s), for optical coupling with the optical waveguide system. An optical element is operatively coupled to the optical waveguide system and positioned in the V-groove fiber optic receptacle. A magnetic force inducer (MFI) is positioned to forcibly direct the optical element into position in the V-groove fiber optic receptacle in response to application of a magnetic field from a direction opposite the V-groove fiber optic receptacle in the first surface. During assembly, a magnetic field may be applied to the MFI to generate the magnetic force. After adhering the optical element, the magnetic field may remain to allow the PIC package to be moved with more security.

Abstract: A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.

Abstract: A connection validation apparatus includes a connector engagement mechanism configured to physically engage a connector to connect the connector to a connector interface. The apparatus further includes a connection indication detector located on the connector engagement mechanism and configured to detect at least one of a sound and a vibration corresponding to a secure connection of the connector with the connector interface. The apparatus also includes a connection indicator output unit configured to provide an indication to a user that the connector is securely connected with the connector interface based on the detection of the at least one of the sound and the vibration by the connection indication detector.

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

Abstract: An interposer structure and a method of interconnecting first and second semiconductor dies are provided. A splice interposer is attached to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor. The height of the second plurality of pillars is greater than the height of the third plurality of pillars. The second semiconductor die is attached to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die.

Abstract: A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.

Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.

Abstract: A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.