Patents by Inventor Benjamin W. Stolt
Benjamin W. Stolt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10664275Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.Type: GrantFiled: August 30, 2018Date of Patent: May 26, 2020Assignee: International Business Machines CorporationInventors: Susan E. Eisen, Hung Q. Le, Bryan J. Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt, Shih-Hsiung S. Tung
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Publication number: 20190012175Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.Type: ApplicationFiled: August 30, 2018Publication date: January 10, 2019Inventors: Susan E. Eisen, Hung Q. Le, Bryan J. Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt, Shih-Hsiung S. Tung
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Patent number: 10067765Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.Type: GrantFiled: May 14, 2012Date of Patent: September 4, 2018Assignee: International Business Machines CorporationInventors: Susan E. Eisen, Hung Q. Le, Bryan J. Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt, Shih-Hsiung S. Tung
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Patent number: 9495170Abstract: During a pipeline stall in a processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from functional units of the processor, finish reports including completion reasons for separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the finish reports. Once the monitoring unit receives a complete indicator from the completion unit, indicating the completion of the next to complete instruction group, the monitoring unit stores each determined stall reason aligned with each next to finish indicator in memory.Type: GrantFiled: December 11, 2013Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Venkat R. Indukuru, Brian R. Konigsburg, Alexander E. Mericas, Benjamin W. Stolt
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Patent number: 9489207Abstract: Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.Type: GrantFiled: April 14, 2009Date of Patent: November 8, 2016Assignee: International Business Machines CorporationInventors: William E. Burky, Brian R. Mestan, Dung Q. Nguyen, Balaram Sinharoy, Benjamin W. Stolt
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Patent number: 9389867Abstract: In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.Type: GrantFiled: August 31, 2015Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Bryan Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt
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Patent number: 9384002Abstract: In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.Type: GrantFiled: November 16, 2012Date of Patent: July 5, 2016Assignee: International Business Machines CorporationInventors: Sundeep Chadha, Bryan Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt
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Publication number: 20150370573Abstract: In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.Type: ApplicationFiled: August 31, 2015Publication date: December 24, 2015Inventors: SUNDEEP CHADHA, BRYAN LLOYD, DUNG Q. NGUYEN, DAVID S. RAY, BENJAMIN W. STOLT
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Patent number: 8874880Abstract: Instructions are tracked in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.Type: GrantFiled: August 26, 2013Date of Patent: October 28, 2014Assignee: International Business Machines CorporationInventors: Christopher M. Abernathy, Hung Q. Le, Dung Q. Nguyen, Benjamin W. Stolt
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Publication number: 20140143523Abstract: In a processor core, high latency operations are tracked in entries of a data structure associated with an execution unit of the processor core. In the execution unit, execution of an instruction dependent on a high latency operation tracked by an entry of the data structure is speculatively finished prior to completion of the high latency operation. Speculatively finishing the instruction includes reporting an identifier of the entry to completion logic of the processor core and removing the instruction from an execution pipeline of the execution unit. The completion logic records dependence of the instruction on the high latency operation and commits execution results of the instruction to an architected state of the processor only after successful completion of the high latency operation.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: SUNDEEP CHADHA, BRYAN LLOYD, DUNG Q. NGUYEN, DAVID S. RAY, BENJAMIN W. STOLT
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Publication number: 20140101416Abstract: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: VENKAT R. INDUKURU, BRIAN R. KONIGSBURG, ALEXANDER E. MERICAS, BENJAMIN W. STOLT
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Patent number: 8635436Abstract: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports.Type: GrantFiled: April 29, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Venkat R. Indukuru, Brian R. Konigsburg, Alexander E. Mericas, Benjamin W. Stolt
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Publication number: 20130346731Abstract: Instructions are tracked in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.Type: ApplicationFiled: August 26, 2013Publication date: December 26, 2013Applicant: International Business Machines CorporationInventors: Christopher M. Abernathy, Hung Q. Le, Dung Q. Nguyen, Benjamin W. Stolt
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Publication number: 20130305022Abstract: Mechanisms are provided, in a processor, for executing instructions that are younger than a previously dispatched synchronization (sync) instruction is provided. An instruction sequencer unit of the processor dispatches a sync instruction. The sync instruction is sent to a nest of one or more devices outside of the processor. The instruction sequencer unit dispatches a subsequent instruction after dispatching the sync instruction. The dispatching of the subsequent instruction after dispatching the sync instruction is performed prior to receiving a sync acknowledgement response from the nest. The instruction sequencer unit performs a completion of the subsequent instruction based on whether completion of the subsequent instruction is dependent upon receiving the sync acknowledgement from the nest and completion of the sync instruction.Type: ApplicationFiled: May 14, 2012Publication date: November 14, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Susan E. Eisen, Hung Q. Le, Bryan J. Lloyd, Dung Q. Nguyen, David S. Ray, Benjamin W. Stolt, Shih-Hsiung S. Tung
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Patent number: 8386753Abstract: A mechanism is provided for thread completion arbitration. The mechanism comprises executing more than two threads of instructions simultaneously in the processor, selecting a first thread from a first subset of threads, in the more than two threads, for completion of execution within the processor, and selecting a second thread from a second subset of threads, in the more than two threads, for completion of execution within the processor. The mechanism further comprises completing execution of the first and second threads by committing results of the execution of the first and second threads to a storage device associated with the processor. At least one of the first subset of threads or the second subset of threads comprise two or more threads from the more than two threads. The first subset of threads and second subset of threads have different threads from one another.Type: GrantFiled: April 14, 2009Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Susan E. Eisen, Dung Q. Nguyen, Balaram Sinharoy, Benjamin W. Stolt
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Publication number: 20120278595Abstract: During a pipeline stall in an out of order processor, until a next to complete instruction group completes, a monitoring unit receives, from a completion unit of a processor, a next to finish indicator indicating the finish of an oldest previously unfinished instruction from among a plurality of instructions of a next to complete instruction group. The monitoring unit receives, from a plurality of functional units of the processor, a plurality of finish reports including completion reasons for a plurality of separate instructions. The monitoring unit determines at least one stall reason from among multiple stall reasons for the oldest instruction from a selection of completion reasons from a selection of finish reports aligned with the next to finish indicator from among the plurality of finish reports.Type: ApplicationFiled: April 29, 2011Publication date: November 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: VENKAT R. INDUKURU, BRIAN R. KONIGSBURG, ALEXANDER E. MERICAS, BENJAMIN W. STOLT
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Patent number: 8131976Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.Type: GrantFiled: April 13, 2009Date of Patent: March 6, 2012Assignee: International Business Machines CorporationInventors: Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt, Jeffrey R. Summers, Albert J. Van Norstrand, Jr.
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Publication number: 20110302392Abstract: A method and apparatus for tracking instructions in a processor. A completion unit in the processor receives an instruction group to add to a table to form a received instruction group. In response to receiving the received instruction group, the completion unit determines whether an entry is present that contains a previously stored instruction group in a first location and has space for storing the received instruction group. In response to the entry being present, the completion unit stores the received instruction group in a second location in the entry to form a stored instruction group.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher M. Abernathy, Hung Q. Le, Dung Q. Nguyen, Benjamin W. Stolt
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Publication number: 20100262807Abstract: Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: William E. Burky, Brian R. Mestan, Dung Q. Nguyen, Balaram Sinharoy, Benjamin W. Stolt
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Publication number: 20100262806Abstract: Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.Type: ApplicationFiled: April 13, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Richard W. Doing, Susan E. Eisen, David S. Levitan, Kevin N. Magill, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt, Jeffrey R. Summers, Albert J. Van Norstrand, JR.