Patents by Inventor Benjamin Walker

Benjamin Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12153962
    Abstract: The disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. The disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Ziye Yang, James R. Harris, Kiran Patil, Benjamin Walker, Sudheer Mogilappagari, Yadong Li, Mark Wunderlich, Anil Vasudevan
  • Patent number: 12118240
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Benjamin Walker, Sanjeev Trika, Kapil Karkra, James R. Harris, Steven C. Miller, Bishwajit Dutta
  • Publication number: 20240296083
    Abstract: Examples relate to an apparatus, device, method, and computer program for providing access to offloading circuitry of a computer system, to a method and computer program for setting up access to offloading circuitry of a computer system, and to corresponding computer systems. The apparatus comprises circuitry configured to provide a common interface for accessing offloading circuitry of the computer system from one or more software applications. The circuitry is configured to select one of a kernel-space driver and a user-space driver for accessing the offloading circuitry. The circuitry is configured to provide the access to the offloading circuitry for the one or more software applications via the selected driver at runtime.
    Type: Application
    Filed: November 25, 2021
    Publication date: September 5, 2024
    Inventors: Ziye YANG, Paul LUSE, James HARRIS, Benjamin WALKER
  • Publication number: 20240264871
    Abstract: The disclosure concerns at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers. The disclosure concerns at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.
    Type: Application
    Filed: March 27, 2024
    Publication date: August 8, 2024
    Applicant: Intel Corporation
    Inventors: Ziye YANG, James R. HARRIS, Kiran PATIL, Benjamin WALKER, Sudheer MOGILAPPAGARI, Yadong LI, Mark WUNDERLICH, Anil VASUDEVAN
  • Publication number: 20240241792
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Patent number: 11971782
    Abstract: Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 30, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20230266459
    Abstract: Described are examples of a method and a system for locating and identifying an object in a search space. The method may be used to determine the presence, identity and relative location of a consumable item. The method uses an array of RFID antennas to interrogate the search space in which one or more objects having an attached RFID tag may be present. The RFID antennas transmit RF signals into the search space and detect RFID reply signals from RFID tags. RFID antennas can be operated at different receiver sensitivity gains or transmit power gains to define additional cell locations within the search space. The identity and location of the objects is determined from the detected RFID reply signals. In various applications, the location is determined in a linear search space, a two-dimensional search space or a three-dimensional search space according to array configuration and gain implementation.
    Type: Application
    Filed: February 21, 2023
    Publication date: August 24, 2023
    Inventors: Micah I. Watt, Benjamin Yeats, Simon Shakespeare, Benjamin Walker, David Pooley, Daniel Crichton
  • Patent number: 11734204
    Abstract: Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Gang Cao, James R. Harris, Ziye Yang, Vishal Verma, Changpeng Liu, Chong Han, Benjamin Walker
  • Publication number: 20230205715
    Abstract: A method is described. The method includes receiving a first invocation for a first ASIC block on a semiconductor chip. The first invocation provides a value. The method includes receiving a second invocation for a second ASIC block on the semiconductor chip. The second invocation also provides the value. The method includes determining that the second ASIC block is to operate on output from the first ASIC block from the first and second invocations having both provided the value. The method includes using a first device driver for the first ASIC block and a second device driver for the ASIC block to cause the second ASIC block to operate on the output from the first ASIC block.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 29, 2023
    Inventors: James R. HARRIS, Benjamin WALKER
  • Publication number: 20230082403
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 20, 2020
    Publication date: March 16, 2023
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20230076365
    Abstract: A method is described. The method includes constructing a bitmap having a first dimension organized into bins of logical block addresses (LBA bins) and a second dimension organized into bins of physical block addresses (PBA bins). Coordinates of the bitmap indicate whether respective physical blocks of non volatile memory within one or more SSDs that fall within a particular PBA bin are being mapped to by an LBA that falls within a particular one of the LBA bins. The method includes using the bitmap during a rebuild of an LBA bin of an LBA/PBA table to avoid reading meta data for physical blocks that are not mapped to by an LBA that falls within the LBA bin.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 9, 2023
    Inventors: James R. HARRIS, Benjamin WALKER, Mateusz Kozlowski, Kapil KARKRA, Artur Paszkiewicz
  • Publication number: 20220121455
    Abstract: Various systems and methods for implementing intent-based cluster administration are described herein. An orchestrator system includes: a processor; and memory to store instructions, which when executed by the processor, cause the orchestrator system to: receive, at the orchestrator system, an administrative intent-based service level objective (SLO) for an infrastructure configuration of an infrastructure; map the administrative intent-based SLO to a set of imperative policies; deploy the set of imperative policies to the infrastructure; monitor performance of the infrastructure; detect non-compliance with the set of imperative policies; and modify the administrative intent-based SLO to generate a revised set of imperative policies that cause the performance of the infrastructure to be compliant with the revised set of imperative policies.
    Type: Application
    Filed: December 23, 2021
    Publication date: April 21, 2022
    Inventors: Adrian Hoban, Thijs Metsch, Francesc Guim Bernat, John J. Browne, Kshitij Arun Doshi, Mark Yarvis, Bin Li, Susanne M. Balle, Benjamin Walker, David Cremins, Mats Gustav Agerstam, Marcos E. Carranza, MIkko Ylinen, Dario Nicolas Oliver, John Mangan
  • Patent number: 11301149
    Abstract: Embodiments of the present disclosure relate to an electronic apparatus that includes a metadata generator, to generate an extents table (ET) that lists one or more extents pages (EPs), where an EP is a fixed size, and where the one or more EPs store one or more extents. An extent includes an allocation indication for a cluster in a memory device, where a number of the extents corresponds to a number of clusters of the memory device, where a subset number of the extents is stored in one of the one or more EPs, and where the subset number is based on the fixed size of the EP. The electronic apparatus further includes a metadata updater, to modify the allocation indication in the extent stored in the one of the one or more EPs, based on a corresponding change in an allocation of the cluster in the memory device.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: James Harris, Benjamin Walker, Tomasz Zawadzki
  • Publication number: 20200363998
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to maintain a respective lookup table for each of two or more persistent storage devices in a persistent memory outside of the two or more persistent storage devices with a first indirection granularity that is smaller than a second indirection granularity of each of the two or more persistent storage devices, buffer write requests to the two or more persistent storage devices in the persistent memory in accordance with the respective lookup tables, and perform a sequential write from the persistent memory to a particular device of the two or more persistent storage devices when a portion of the buffer that corresponds to the particular device has an amount of data to write that corresponds to the second indirection granularity. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Applicant: Intel Corporation
    Inventors: Benjamin Walker, Sanjeev Trika, Kapil Karkra, James R. Harris, Steven C. Miller, Bishwajit Dutta
  • Patent number: 10770179
    Abstract: An optimal sample size for experiments targeting units having specific static criteria is determined, based on one or more iterations of a performed experiment. The sample size to use for subsequent experiments targeting units having the specific static criteria is calculated based on target effect of the performed experiment. Multiple iterations can be performed to refine the sample size. Each iteration uses the previously calculated sample size as a parameter. The calculated sample size is then used to determine an optimal treatment. Separate experiments using separate treatments are performed on separate group sets of the calculated sample size. For each separate performed experiment, a score is calculated for the corresponding specific treatment, taking into account actual effect size, statistical significance and homogeneity of effect. Depending upon the score, the given treatment can be accepted for production usage or discarded, or the experiment can be replicated to validate effect.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 8, 2020
    Assignee: JUNTOS, INC.
    Inventors: Christopher Benjamin Walker, Dante Emilio Cassanego
  • Publication number: 20200241927
    Abstract: Examples described herein relate to at least one processor that can execute a polling group to poll for storage transactions associated with a first group of one or more particular queue identifiers, wherein the one or more particular queue identifiers are associated with one or more queues that can be accessed using the polling group and no other polling group. In some examples, the polling group is to execute on a processor that runs no other polling group. In some examples, the at least one processor is configured to: execute a second polling group on a second processor, wherein the second polling group is to poll for storage transactions for a second group of one or more particular queue identifiers that are different than the one or more particular queue identifiers of the first group, wherein the second group of one or more particular queue identifiers are associated with one or more queues that can be accessed using the second polling group and not the first polling group.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Inventors: Ziye YANG, James R. HARRIS, Kiran PATIL, Benjamin WALKER, Sudheer MOGILAPPAGARI, Yadong LI, Mark WUNDERLICH, Anil VASUDEVAN
  • Publication number: 20200218676
    Abstract: Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Inventors: Gang CAO, James R. HARRIS, Ziye YANG, Vishal VERMA, Changpeng LIU, Chong HAN, Benjamin WALKER
  • Patent number: 10445260
    Abstract: Methods of accessing hardware input/output (I/O) queues by software threads performing operations on a storage system, such as a filesystem, are described herein. In one embodiment, a method for performing I/O operations on a filesystem stored at least in part on a storage device involves creating a channel to map exclusively to one hardware I/O queue of the storage device. The channel includes an instance of a software primitive in the filesystem to route I/O requests to access objects in the filesystem from an application executing on one or more threads to the one hardware I/O queue to which the channel maps. The method also involves submitting the I/O requests to access the objects in the filesystem from at most one thread of the application at a given time to the one hardware I/O queue using the channel.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Benjamin Walker, Daniel R. Verkamp
  • Publication number: 20190205052
    Abstract: Embodiments of the present disclosure relate to an electronic apparatus that includes a metadata generator, to generate an extents table (ET) that lists one or more extents pages (EPs), where an EP is a fixed size, and where the one or more EPs store one or more extents. An extent includes an allocation indication for a cluster in a memory device, where a number of the extents corresponds to a number of clusters of the memory device, where a subset number of the extents is stored in one of the one or more EPs, and where the subset number is based on the fixed size of the EP. The electronic apparatus further includes a metadata updater, to modify the allocation indication in the extent stored in the one of the one or more EPs, based on a corresponding change in an allocation of the cluster in the memory device.
    Type: Application
    Filed: March 7, 2019
    Publication date: July 4, 2019
    Inventors: James Harris, Benjamin Walker, Tomasz Zawadzki
  • Patent number: D998970
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 19, 2023
    Inventor: Benjamin Walker Snell