Abstract: Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.

Abstract: Techniques regarding nanofluidic chips with a plurality of inlets and/or outlets in fluid communication with one or more nanoDLD arrays are provided. For example, one or more embodiments described herein can comprise a nanoscale deterministic lateral displacement array between and in fluid communication with a global inlet and a global outlet. The nanoscale deterministic lateral displacement array can further be between and in fluid communication with a local inlet and a local outlet. Also, the nanoscale deterministic lateral displacement array can laterally displace a particle comprised within a sample fluid supplied from the global inlet to a collection region that directs the particle to the local outlet. An advantage of such an apparatus can be the expanded versatility of the nanoscale deterministic lateral displacement array for sample preparation applications involving nanoparticles not accessible to other higher throughput microscale microfluidic technologies.

Abstract: Techniques regarding one or more structures that can facilitate automated, multi-stage processing of one or more nanofluidic chips are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a roller positioned adjacent to a microfluidic card comprising a plurality of fluid reservoirs in fluid communication with a plurality of nanofluidic chips. An arrangement of the plurality of nanofluidic chips on the microfluidic card can defines a processing sequence driven by a translocation of the roller across the microfluidic card.

Abstract: Techniques regarding screening for mutations using nanoscale deterministic arrays are provided. For example, one or more embodiments described herein can comprise a method, which can comprise cleaving a deoxyribonucleic acid segment hybridized with a molecular probe to form a sample fluid. The cleaving can occur at a first end and a second end of the molecular probe. Also, the cleaving can comprise a cleaving agent that targets base pair mismatches. The method can also comprise supplying the sample fluid to a nanoscale deterministic lateral displacement array to screen for a single nucleotide polymorphism.

Abstract: An exemplary method includes forming a sacrificial layer along sidewalls of an array of trenches that are indented into a substrate, depositing a fill layer over the sacrificial layer, and then creating an array of gaps between the fill layer and the substrate by removing the sacrificial layer along the sidewalls of the trenches, while maintaining a structural connection between the substrate and the fill layer at the floors of the trenches. The method further includes covering the substrate, the fill layer, and the gaps with a cap layer that seal fluid-tight against the substrate and the fill layer. The method further includes indenting a first reservoir and a second reservoir through the cap layer, and into the substrate and the fill layer, across the lengths of the array of gaps, so that the array of gaps connects the first reservoir in fluid communication with the second reservoir.

Abstract: A fluidic processor device and a wafer including the same, the device including a nanofluidic separator chip including a nanoDLD array, a housing for housing the chip including a top plate disposed on a topside of the chip, a bottom plate disposed on a backside of the chip and fastened to the top plate, and a spacer disposed between the chip and the bottom plate to create a clearance between the chip and the bottom plate for forming a drain space on the backside of the chip.

Abstract: A method for fabricating a fluidic device includes depositing a sacrificial material on a pillar array arranged on a substrate. The method also includes removing a portion of the sacrificial material. The method further includes depositing a sealing layer on the pillar array to form a sealed fluidic cavity.

Abstract: Techniques regarding integrated purification-detection devices for detecting one or more biomarkers are provided. For example, one or more embodiments described herein are directed to an apparatus, comprising a housing and a microfluidic chip contained within the housing. The microfluidic chip comprises a separation unit that separates, using one or more nano deterministic lateral displacement (nanoDLD) arrays, target biological entities having a defined size range from other biological entities included in a biological fluid sample. The microfluidic chip further comprises a detection unit that facilitates detecting presence of one or more biomarkers associated with the target biological entities using one or more detection molecules or macromolecules that chemically reacts with the one or more biomarkers.

Abstract: Techniques regarding nanofluidic chips with a plurality of inlets and/or outlets in fluid communication with one or more nanoDLD arrays are provided. For example, one or more embodiments described herein can comprise a nanoscale deterministic lateral displacement array between and in fluid communication with a global inlet and a global outlet. The nanoscale deterministic lateral displacement array can further be between and in fluid communication with a local inlet and a local outlet. Also, the nanoscale deterministic lateral displacement array can laterally displace a particle comprised within a sample fluid supplied from the global inlet to a collection region that directs the particle to the local outlet. An advantage of such an apparatus can be the expanded versatility of the nanoscale deterministic lateral displacement array for sample preparation applications involving nanoparticles not accessible to other higher throughput microscale microfluidic technologies.

Abstract: Techniques regarding nanofluidic chips with a plurality of inlets and/or outlets in fluid communication with one or more nanoDLD arrays are provided. For example, one or more embodiments described herein can comprise a nanoscale deterministic lateral displacement array between and in fluid communication with a global inlet and a global outlet. The nanoscale deterministic lateral displacement array can further be between and in fluid communication with a local inlet and a local outlet. Also, the nanoscale deterministic lateral displacement array can laterally displace a particle comprised within a sample fluid supplied from the global inlet to a collection region that directs the particle to the local outlet. An advantage of such an apparatus can be the expanded versatility of the nanoscale deterministic lateral displacement array for sample preparation applications involving nanoparticles not accessible to other higher throughput microscale microfluidic technologies.

Abstract: A method for fabricating a fluidic device includes depositing a sacrificial material on a pillar array arranged on a substrate. The method also includes removing a portion of the sacrificial material. The method further includes depositing a sealing layer on the pillar array to form a sealed fluidic cavity.

Abstract: A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.

Abstract: Techniques regarding one or more structures that can facilitate automated, multi-stage processing of one or more nanofluidic chips are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a roller positioned adjacent to a microfluidic card comprising a plurality of fluid reservoirs in fluid communication with a plurality of nanofluidic chips. An arrangement of the plurality of nanofluidic chips on the microfluidic card can defines a processing sequence driven by a translocation of the roller across the microfluidic card.

Abstract: A method for fabricating a fluidic device includes depositing a sacrificial material on a pillar array arranged on a substrate. The method also includes removing a portion of the sacrificial material. The method further includes depositing a sealing layer on the pillar array to form a sealed fluidic cavity.

Abstract: Techniques regarding one or more structures that can facilitate automated, multi-stage processing of one or more nanofluidic chips are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a roller positioned adjacent to a microfluidic card comprising a plurality of fluid reservoirs in fluid communication with a plurality of nanofluidic chips. An arrangement of the plurality of nanofluidic chips on the microfluidic card can defines a processing sequence driven by a translocation of the roller across the microfluidic card.

Abstract: Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.

Abstract: Techniques regarding microfluidic chips with one or more vias filled with sacrificial plugs and/or manufacturing methods thereof are provided herein. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a silicon device layer of a microfluidic chip comprising a plurality of vias extending through the silicon device layer. The plurality of vias comprise greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer. Additionally, the apparatus can comprise a plurality of sacrificial plugs positioned in the plurality of vias.

Abstract: Techniques regarding one or more structures for checking the via formation are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a microfluidic channel positioned on a silicon substrate. The apparatus can also comprise a pattern of material comprised within the microfluidic channel and positioned on a surface of the silicon substrate. Further, the pattern of material can define a future location of a through-silicon via. An advantage of such an apparatus can be that the pattern of material can facilitate checking whether the through-silicon via is fully or partially formed.

Abstract: An exemplary method includes forming a sacrificial layer along sidewalls of an array of trenches that are indented into a substrate, depositing a fill layer over the sacrificial layer, and then creating an array of gaps between the fill layer and the substrate by removing the sacrificial layer along the sidewalls of the trenches, while maintaining a structural connection between the substrate and the fill layer at the floors of the trenches. The method further includes covering the substrate, the fill layer, and the gaps with a cap layer that seal fluid-tight against the substrate and the fill layer. The method further includes indenting a first reservoir and a second reservoir through the cap layer, and into the substrate and the fill layer, across the lengths of the array of gaps, so that the array of gaps connects the first reservoir in fluid communication with the second reservoir.

Abstract: Techniques regarding screening for mutations using nanoscale deterministic arrays are provided. For example, one or more embodiments described herein can comprise a method, which can comprise cleaving a deoxyribonucleic acid segment hybridized with a molecular probe to form a sample fluid. The cleaving can occur at a first end and a second end of the molecular probe. Also, the cleaving can comprise a cleaving agent that targets base pair mismatches. The method can also comprise supplying the sample fluid to a nanoscale deterministic lateral displacement array to screen for a single nucleotide polymorphism.