Patents by Inventor Benjamin Wymore
Benjamin Wymore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12099899Abstract: A method of increasing grain size of polycrystalline superconducting materials for superconducting circuits, includes forming an initial superconducting epitaxial layer lattice matched to a substrate formed of a substrate material, the initial superconducting epitaxial layer formed of a compound including the substrate material and a first metal; and forming a second layer of the first metal on the initial superconducting epitaxial layer and heating the layers to increase a thickness of the initial superconducting epitaxial layer formed of the compound.Type: GrantFiled: July 31, 2020Date of Patent: September 24, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Sweet Jean L.
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Patent number: 12102016Abstract: Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element.Type: GrantFiled: July 1, 2020Date of Patent: September 24, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Stephen L Brown
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Publication number: 20230397506Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.Type: ApplicationFiled: August 22, 2023Publication date: December 7, 2023Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, Keith E. Fogel, John Bruley, Markus Brink, Benjamin Wymore
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Patent number: 11765985Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.Type: GrantFiled: June 22, 2020Date of Patent: September 19, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, Keith Fogel, John Bruley, Markus Brink, Benjamin Wymore
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Patent number: 11552237Abstract: A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.Type: GrantFiled: August 19, 2020Date of Patent: January 10, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin Wymore, Christian Lavoie, Markus Brink, John Bruley
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Patent number: 11495724Abstract: A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.Type: GrantFiled: July 21, 2020Date of Patent: November 8, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjamin Wymore, Christian Lavoie, Markus Brink
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Patent number: 11480537Abstract: A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.Type: GrantFiled: July 31, 2020Date of Patent: October 25, 2022Assignee: International Business Machines CorporationInventors: Christian Lavoie, Markus Brink, Benjamin Wymore, Jeng-Bang Yau
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Publication number: 20220059748Abstract: A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.Type: ApplicationFiled: August 19, 2020Publication date: February 24, 2022Inventors: Benjamin Wymore, Christian Lavoie, Markus Brink, John Bruley
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Publication number: 20220034833Abstract: A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Inventors: Christian Lavoie, Markus Brink, Benjamin Wymore, Jeng-Bang Yau
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Publication number: 20220036228Abstract: A method of increasing grain size of polycrystalline superconducting materials for superconducting circuits, includes forming an initial superconducting epitaxial layer lattice matched to a substrate formed of a substrate material, the initial superconducting epitaxial layer formed of a compound including the substrate material and a first metal; and forming a second layer of the first metal on the initial superconducting epitaxial layer and heating the layers to increase a thickness of the initial superconducting epitaxial layer formed of the compound.Type: ApplicationFiled: July 31, 2020Publication date: February 3, 2022Inventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Sweet Jean L.
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Publication number: 20220029083Abstract: A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.Type: ApplicationFiled: July 21, 2020Publication date: January 27, 2022Inventors: Benjamin Wymore, Christian Lavoie, Markus Brink
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Publication number: 20220005999Abstract: Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element.Type: ApplicationFiled: July 1, 2020Publication date: January 6, 2022Inventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Stephen L. Brown
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Publication number: 20210399199Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.Type: ApplicationFiled: June 22, 2020Publication date: December 23, 2021Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, Keith Fogel, John Bruley, Markus Brink, Benjamin Wymore
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Patent number: 11024512Abstract: Enhanced compositions and methods are provided for selectively etching silicon wafers, which is particularly useful in the context of silicon wafer manufacturing and processing applications. Optionally, a formulation is provided which selectively etches silicon dioxide in preference to aluminum oxide. Optionally, a formulation and method are provided that is substantially non-aqueous.Type: GrantFiled: March 6, 2020Date of Patent: June 1, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ali Afzali-Ardakani, Benjamin Wymore, David L. Rath, George G. Totir
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Patent number: 10192971Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.Type: GrantFiled: January 30, 2017Date of Patent: January 29, 2019Assignee: NUtech VenturesInventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore
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Publication number: 20170141202Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.Type: ApplicationFiled: January 30, 2017Publication date: May 18, 2017Inventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore
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Patent number: 9558929Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.Type: GrantFiled: November 25, 2014Date of Patent: January 31, 2017Assignee: NUtech VenturesInventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore
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Publication number: 20150170906Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.Type: ApplicationFiled: November 25, 2014Publication date: June 18, 2015Inventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore