Patents by Inventor Benjamin Wymore

Benjamin Wymore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12099899
    Abstract: A method of increasing grain size of polycrystalline superconducting materials for superconducting circuits, includes forming an initial superconducting epitaxial layer lattice matched to a substrate formed of a substrate material, the initial superconducting epitaxial layer formed of a compound including the substrate material and a first metal; and forming a second layer of the first metal on the initial superconducting epitaxial layer and heating the layers to increase a thickness of the initial superconducting epitaxial layer formed of the compound.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 24, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Sweet Jean L.
  • Patent number: 12102016
    Abstract: Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 24, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Stephen L Brown
  • Publication number: 20230397506
    Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.
    Type: Application
    Filed: August 22, 2023
    Publication date: December 7, 2023
    Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, Keith E. Fogel, John Bruley, Markus Brink, Benjamin Wymore
  • Patent number: 11765985
    Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 19, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, Keith Fogel, John Bruley, Markus Brink, Benjamin Wymore
  • Patent number: 11552237
    Abstract: A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: January 10, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin Wymore, Christian Lavoie, Markus Brink, John Bruley
  • Patent number: 11495724
    Abstract: A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin Wymore, Christian Lavoie, Markus Brink
  • Patent number: 11480537
    Abstract: A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: October 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Markus Brink, Benjamin Wymore, Jeng-Bang Yau
  • Publication number: 20220059748
    Abstract: A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.
    Type: Application
    Filed: August 19, 2020
    Publication date: February 24, 2022
    Inventors: Benjamin Wymore, Christian Lavoie, Markus Brink, John Bruley
  • Publication number: 20220034833
    Abstract: A method of measuring contact resistance at an interface for superconducting circuits is provided. The method includes using a chain structure of superconductors to measure a contact resistance at a contact between contacting superconductor. The method further includes eliminating ohmic resistance from wire lengths in the chain structure by operating below the lowest superconducting transition temperature of all the superconductors in the chain structure. The measurement is dominated by contact resistances of the contacts between contacting superconductors in the chain.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: Christian Lavoie, Markus Brink, Benjamin Wymore, Jeng-Bang Yau
  • Publication number: 20220036228
    Abstract: A method of increasing grain size of polycrystalline superconducting materials for superconducting circuits, includes forming an initial superconducting epitaxial layer lattice matched to a substrate formed of a substrate material, the initial superconducting epitaxial layer formed of a compound including the substrate material and a first metal; and forming a second layer of the first metal on the initial superconducting epitaxial layer and heating the layers to increase a thickness of the initial superconducting epitaxial layer formed of the compound.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Sweet Jean L.
  • Publication number: 20220029083
    Abstract: A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.
    Type: Application
    Filed: July 21, 2020
    Publication date: January 27, 2022
    Inventors: Benjamin Wymore, Christian Lavoie, Markus Brink
  • Publication number: 20220005999
    Abstract: Techniques facilitating formation of amorphous superconducting alloys for superconducting circuits are provided. A device can comprise one or more superconducting components that comprise an amorphous superconducting alloy comprising two or more elements. At least one element of the two or more elements is a superconducting element.
    Type: Application
    Filed: July 1, 2020
    Publication date: January 6, 2022
    Inventors: Christian Lavoie, Benjamin Wymore, Markus Brink, Stephen L. Brown
  • Publication number: 20210399199
    Abstract: Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 23, 2021
    Inventors: Vivekananda P. Adiga, Martin O. Sandberg, Jeng-Bang Yau, Keith Fogel, John Bruley, Markus Brink, Benjamin Wymore
  • Patent number: 11024512
    Abstract: Enhanced compositions and methods are provided for selectively etching silicon wafers, which is particularly useful in the context of silicon wafer manufacturing and processing applications. Optionally, a formulation is provided which selectively etches silicon dioxide in preference to aluminum oxide. Optionally, a formulation and method are provided that is substantially non-aqueous.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ali Afzali-Ardakani, Benjamin Wymore, David L. Rath, George G. Totir
  • Patent number: 10192971
    Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: January 29, 2019
    Assignee: NUtech Ventures
    Inventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore
  • Publication number: 20170141202
    Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.
    Type: Application
    Filed: January 30, 2017
    Publication date: May 18, 2017
    Inventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore
  • Patent number: 9558929
    Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: January 31, 2017
    Assignee: NUtech Ventures
    Inventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore
  • Publication number: 20150170906
    Abstract: A top-gated graphene field effect transistor can be fabricated by forming a layer of graphene on a substrate, and applying an electrochemical deposition process to deposit a layer of dielectric polymer on the graphene layer. An electric potential between the graphene layer and a reference electrode is cycled between a lower potential and a higher potential. A top gate is formed above the polymer.
    Type: Application
    Filed: November 25, 2014
    Publication date: June 18, 2015
    Inventors: Jody G. Redepenning, Alexander Sinitskii, Benjamin Wymore