Abstract: A digital system has a resource, such as a communication bus, adapted for access by a plurality of devices, a plurality of devices adapted to access the resource, and an arbitrator for arbitrating access to the resource by the devices. The arbitrator includes a programmable memory comprising a plurality of addressable words and an address generator for cyclically sequentially addressing each of the memory words. Each word stores information defining a priority order of the devices for accessing the resource. In particular, each word is divided into a plurality of segments, and each segment corresponds with a priority level in the order of priority. Each segment holds information identifying the device currently having the corresponding priority level. The priority order is changeable by reprogramming the contents of the memory. The priority order so implemented may be any conceivable order, and in particular may include a constant decreasing priority, a round-robin priority, or a combination of the two.

Abstract: In a programmable system (10) which includes a processor (11) for executing a program structured from a plurality of subprograms, and a stack cache memory (16) for storing subprogram linkage information, the stack (41) is comprised of frames (40) of equal size. Each frame (40) stores the information linking a subprogram to the immediately preceding subprogram. A set of general registers (44) is implemented in each frame (40). Preferably each frame (40) is comprised of a plurality of blocks (42-45) of an equal number of cache memory words (46). The set of general registers (44) occupies one block (44) of the frame (40).Addressing of individual words (46) in a frame (40) is accomplished via concatenation of a frame pointer (18, 19, 32) a block selector (51, 33), and a word selector (52, 34). Preferably a second memory (12), such as a portion of a main memory, is also included in the system (10) and stores linkage information, such as overflow linkage information.

Abstract: A cache memory system reduces cache interference during direct memory access block write operations to main memory. A control memory within cache contains in a single location validity bits for each word in a memory block. In response to the first word transferred at the beginning of a direct memory access block write operation to main memory, all validity bits for the block are reset in a single cache cycle. Cache is thereafter free to be read by the central processor during the time that the remaining words of the block are written without the need for additional cache invalidation memory cycles.