Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: The invention discloses an apparatus for measuring the torsion between a first point (41) and a second point (42) of a test object (1), said second point being spaced apart from the first point.

Abstract: The invention discloses an apparatus for measuring the torsion between a first point (41) and a second point (42) of a test object (1), said second point being spaced apart from the first point.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: An exemplary data center architecture includes a services abstraction, a data sources abstraction, an internal applications abstraction and a core administration abstraction for static and dynamic enforcement of data center polices based on compliance with a property set, a specification set or a property set and a specification set. Such an architecture can include a core administration abstraction with logic to install services and to upgrade services in a data center where a service must comply with the property set and the specification set prior to installation of the service or upgrade of the service in the data center. Various other devices, systems and methods are also described.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.

Abstract: An exemplary data center architecture includes a services abstraction, a data sources abstraction, an internal applications abstraction and a core administration abstraction for static and dynamic enforcement of data center polices based on compliance with a property set, a specification set or a property set and a specification set. Such an architecture can include a core administration abstraction with logic to install services and to upgrade services in a data center where a service must comply with the property set and the specification set prior to installation of the service or upgrade of the service in the data center. Various other devices, systems and methods are also described.

Abstract: Described herein is at least one implementation employing multiple self-describing software artifacts persisted on one or more computer-storage media of a software-based computer. In this implementation, each artifact is representative of at least part of the software components (e.g., load modules, processes, applications, and operating system components) of the computing system and each artifact is described by at least one associated “manifest,” which include metadata declarative descriptions of the associated artifact.

Abstract: Improved robustness of software program executions is achieved via randomization of their execution contexts. For instance, errors related to runtime allocation of memory on the heap can be probabilistically addressed by generating an approximation of the infinite heap and using a randomized memory manager to allocate memory on the heap. In addition to stand alone randomization, several replicas of a software program are executed, each with a memory manager configured with different randomization seeds for randomly allocating memory on an approximation of an infinite heap. Outputs of correctly executing instances of the replicas are determined by accepting the output that at least two of the replicas agree upon.

Abstract: Software program robustness is improved by successfully masking memory safety errors in the software program. For instance, at least some memory safety errors in a software program can be masked by using a runtime memory manager that approximates the semantics of an infinite heap memory manager. In one example, an approximation of an infinite heap memory manager is implemented by configuring a parameterized memory manager with parameter values such as padding to be added to each allocation on the heap and the amount of deferment before executing a call to free memory on the heap. Ideal configurations balance expected robustness with costs such as added memory and processing time. Ideal configurations can be identified through systematic search of a coordinate space of selected parameters. Ideal configurations can also be identified by statistically correlating success/failure data collected from execution of deployed instances of the software program to the configuration of the memory managers used therein.

Abstract: Described herein are methods and systems for providing software development services more efficiently. Re-computation of results each time a service request is received can be avoided by maintaining a cache of results from having processed requests. Results are stored under a unique mapping of request-results pairs that at least in part rely on a file fingerprint hash of the contents of the input files related to the request. In network environment with a client requester and service provider unnecessary transmission is also avoided by first presenting results for requests are in form of a unique file identifier identifying one or more files holding the content of the results. The file identifier is used to search a cache local to the requesting client prior to requesting transmission of the results. The file identifier may also include an indicator for indicating a location from which the results may be retrieved.

Abstract: Described herein are methods and systems for providing software development services in a networked software development environment. For instance, instead of performing compilation on a stand-alone desktop computer, software development activities including, compilation are performed by a service provider in response to a general query from a client requester. Such a network desirably has a global view of the source files being processed by various software development tools associated therewith. This global view enables many interesting approaches including the ability to perform analysis and optimizations to the input files not specified by the client requester. Such anticipatory processing may be based on the history and pattern of previous requests and availability of software development tools that the client requester is not aware of, for instance.