Abstract: A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.

Abstract: An information handling system includes instruction processing nodes in respective physical partitions. A communications bus couples two information processing nodes together. Each node includes hardware resources such as CPUs, memories and I/O adapters. Prior to a command to merge the physical partitions, the communication bus exhibits a disabled state such that the two information processing nodes are effectively disconnected. After receiving a command to merge the physical partitions, the system enables the communication bus to effectively hot-plug the two nodes together. A modified master hypervisor in one node stores data structures detailing the hardware resources of the two nodes. The modified master may assign resources from one node to a logical partition in another node.

Abstract: An information handling system includes instruction processing nodes in respective physical partitions. A communications bus couples two information processing nodes together. Each node includes hardware resources such as CPUs, memories and I/O adapters. Prior to a command to merge the physical partitions, the communication bus exhibits a disabled state such that the two information processing nodes are effectively disconnected. After receiving a command to merge the physical partitions, the system enables the communication bus to effectively hot-plug the two nodes together. A modified master hypervisor in one node stores data structures detailing the hardware resources of the two nodes. The modified master may assign resources from one node to a logical partition in another node.

Abstract: A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the processing system to be dynamically enabled/disabled. When a sequence of instructions constituting a data move operation is being issued, the architected bit is toggled to an interrupt disabled state so that execution of the sequence of instructions occurs without an external interrupt. Following the execution of the sequence of instructions, the architected bit is toggled to an interrupt enabled state, which causes instruction execution to be subjected to external interrupts.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

Abstract: A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

Abstract: A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

Abstract: A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.

Abstract: A method, apparatus, and program for systematically testing the functionality of all connections in a multi-tiered bus system that connects a large number of processors. Each bus controller is instructed to send a test version of a snoop request to all of the other processors and to wait for the replies. If a connection is bad, the port associated with that connection will time out. Detection of a time-out will cause the initialization process to be halted until the problem can be isolated and resolved.

Abstract: A method for enabling concurrent, overlapping data moves associated with separate data clone operations of different memory cloners. A first data is being moved from its source to a destination. The first data is tagged with the address of the first destination to identify the data, and the data is sent over the fabric with the destination tag. A second data is concurrently (or subsequently) routed over the fabric to a next destination, while the first data is still in on the fabric. The second data is also tagged with its specific destination tag, which is different from the destination tag of the first data routed. Thus, the two sets of data overlap on the on the fabric but are each uniquely identified by their respective destination tag. Both the first and second data may also be tagged with a respective unique identifier (ID) associated with the memory cloner that initiated the particular clone operation.

Abstract: Disclosed is a data processing system that completes a data clone operation by routing the directly from a source location within said memory subsystem to a destination location within said memory subsystem. The data is not routed through the processor that initiated the data clone operation. The various storage components of the memory subsystem are directly interconnected to each other via a switch. The switch provides a large bandwidth for routing data. When a data clone operation is issued by the processor on the fabric of the data processing system, the data read operation sent to said source address is modified to include the destination address in place of the processor address. The switch routes the data to the address provided within the data read operation. Thus, the switch automatically routes the data to the destination address rather than to the processor address.

Abstract: A processor chip with a high speed memory cloner that enables movement of data directly from one memory location (of a data processing system) to another without the data having to be routed through the processor. The memory cloner includes processing logic that enables the release of the processor to continue processing other operations while the data are physically moved in the background. The memory cloner generates a sequence of naked writes (i.e., write operations with no data tenure) from the write data commands and forwards the naked writes to the memory controller of the destination memory module. When all the naked write operations receive a Null response (i.e., a response indicating that the specific addressed at the memory module are reserved/set to receive data), the memory cloner signals the processor that the move request is completed.

Abstract: A method for avoiding livelock within a multiprocessor data processing system when there are multiple, concurrent clone operations to similar memory data locations within a data processing system. A set of tokens are defined within the memory cloner for use prior to conducting a clone operation on the fabric. The tokens include a source token and a destination token. The tokens are issued on the fabric by a memory cloner prior to initiating the data clone operation. The tokens discover the availability of a source address and a destination address required to complete the clone operation. Once the response to the destination address token indicates that the destination address is not currently being utilized by another memory cloner to conduct another data clone operation, the memory cloner may issue the commands to initiate the memory clone operation.

Abstract: A method for reserving memory buffers for receiving data prior to the actual movement of data on a data processing system. A naked write operation is generated that includes a destination address and an address of the processor generating the write operation. The naked write operation is then issued on the fabric of said data processing system without any accompanying data. The naked write operation is snooped by the memory controller associated with the destination address. The memory controller then provides a response that is sent to the processor. The response sent depends on whether the memory controller is able to allocate a buffer to the naked write operation. When the memory controller is able to allocate a buffer to the naked write operation, the memory controller issues a Null response, which triggers a read operation that sends the corresponding data to the buffer at a later time.

Abstract: A processing state that enables a processor to resume processing operations before completion of a processor-issued data move operation. The processor executes instructions specifying a data clone operation and delays subsequent instruction execution while waiting for a receipt of an indication that the data clone operation has completed. In response to the instructions, a memory cloner issues a series of naked write operations targeting the destination memory location and tracks receipt of Null responses for each of the naked write operations. When a Null response has been received for each of the naked write operations, the memory cloner transmits an acknowledgment to the processor indicating that the write operation is architecturally complete before the actual data move has completed. In response to receiving the acknowledgment, the processor resumes execution of subsequent instructions in the instruction stream.

Abstract: A data processing system that includes a mode/reserve bit utilized to dynamically change a processor's operating mode between a virtual addressing mode and a real addressing mode. Each address block includes a reserve bit that indicates whether real or virtual addressing is desired, and the reserve bit is assigned a value by the software application executing on the processor. The value of the reserve bit is dynamically set and signals the processor which operating mode is required for the particular address block. The selection of virtual or real addressing mode is determined by the particular application that is being executed by the processor. When the particular application process seeks increased performance rather than protection, the virtual operating mode is selected, allowing the application process to send the effective addresses directly to the OS and hypervisor. This is accomplished by setting the reserve bit to the value for virtual addressing mode.

Abstract: A data processing system comprising a coherency protocol that indicates and updates a coherency state of all data lines within said memory subsystem, and responsive to a naked write operation to a memory location containing a modified copy of data, changes the coherency state of the memory location from modified (M) to invalid (I) without initiating a push of the data to a corresponding address location of main memory. Included within the coherency protocol are specific group of responses for dealing with a naked write request that is received at a memory controller. These responses include: (1) issuing a retry response when the memory controller is unable to allocate a buffer for the write data operation and data at said memory location is not in an M state; (2) issuing a Null response when the memory controller is able to allocate the buffer; and (3) issuing a combined Ack_Resend response when the data at the memory location transitions from an M state to an I state.

Abstract: A processor chip with a high speed memory cloner that enables movement of data directly from one memory location (of a data processing system) to another without the data having to be routed through the processor. The memory cloner includes processing logic that enables the release of the processor to continue processing other operations while the data are physically moved in the background. The memory cloner generates a sequence of naked writes (i.e., write operations with no data tenure) from the write data commands and forwards the naked writes to the memory controller of the destination memory module. When all the naked write operations receive a Null response (i.e., a response indicating that the specific addressed at the memory module are reserved/set to receive data), the memory cloner signals the processor that the move request is completed.

Abstract: A data processing system comprising a coherency protocol that indicates and updates a coherency state of all data lines within said memory subsystem, and responsive to a naked write operation to a memory location containing a modified copy of data, changes the coherency state of the memory location from modified (M) to invalid (I) without initiating a push of the data to a corresponding address location of main memory. Included within the coherency protocol are specific group of responses for dealing with a naked write request that is received at a memory controller. These responses include: (1) issuing a retry response when the memory controller is unable to allocate a buffer for the write data operation and data at said memory location is not in an M state; (2) issuing a Null response when the memory controller is able to allocate the buffer; and (3) issuing a combined Ack_Resend response when the data at the memory location transitions from an M state to an I state.

Abstract: A method for enabling concurrent, overlapping data moves associated with separate data clone operations of different memory cloners. A first data is being moved from its source to a destination. The first data is tagged with the address of the first destination to identify the data, and the data is sent over the fabric with the destination tag. A second data is concurrently (or subsequently) routed over the fabric to a next destination, while the first data is still in on the fabric. The second data is also tagged with its specific destination tag, which is different from the destination tag of the first data routed. Thus, the two sets of data overlap on the on the fabric but are each uniquely identified by their respective destination tag. Both the first and second data may also be tagged with a respective unique identifier (ID) associated with the memory cloner that initiated the particular clone operation.