Abstract: The present invention is directed to a system having a shared processing resource, a plurality of processing modules and a synchronization control module. The shared processing resource is configured to perform processing operations in connection with input data provided by the processing modules, in response to a start indication. Each of the processing modules is configured to perform selected processing operations. At least one of the processing modules is configured to provide input data to the shared processing resource. Each processing module that provides input data is configured to generate a hold indication and to provide the input data to the shared processing resource in response to a synchronization barrier lock. Each processing module is configured to generate a start enable indication. Each processing module that provides input data generates a start enable indication after providing the input data.

Abstract: A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment element. The plurality of circuit elements define a plurality of clock domains, and circuit elements in each clock domain perform processing operations under control of a respective domain clock signal. The scan chain establishment element interconnects the circuit elements in a scan chain to facilitate loading and/or retrieval of a scan vector into and/or out of the digital circuit device. The unitary clock domain establishment element establishes a unitary clock domain for the circuit element when the scan chain establishment element is interconnecting the circuit elements in a scan chain.

Abstract: A base test class is defined in an object-oriented computer program development environment and members of the base test class, i.e., test objects, represent individual test processes in a computer. The base test class defines a number of attributes and member functions which are inherited by test objects including a constructor member function which is performed when a test object is created. Creation of a test object performs substantially all that is required to implement interfaces and protocols (i) for interaction between the test object and simulation systems, (ii) for synchronization of processing of the test object with processing of other test objects and with simulation systems, and (iii) for reservation by the test object of devices of simulation systems. In addition, a base device class defines a number of attributes and member functions which are inherited by device objects. Device objects represent devices of simulation systems which interact with the test process.

Abstract: An interface subsystem for use in a system including one or more simulation systems facilitates simulation of one or more simulation models under control of one or more tests. The interface subsystem allows the tests and simulation systems to transfer information therebetween and enables said tests to control the simulation systems in simulating the simulation model during a simulation run. The simulation systems include transactors which provide information to the simulation model at the beginning of a simulation run, pause a simulation run in response to detection of a selected event, and generate simulation result information. The interface subsystem includes, associated with each test, a simulation information generator, a simulation control indicator generator, and a information receiver; associated with each simulation system an information receiver associated with each transactor and a simulator interface module; and an interface core.