Abstract: An integrated circuit package (50) is provided which comprises a substrate (20), an integrated circuit (12) mounted on the substrate, and a compressive, thermally conductive interposer (52) mounted on the integrated circuit.

Abstract: Integrated circuit packaging with improved thermal transmission from the integrated circuit heat source to the exterior of the packaging. Improved packaging employs a compressive interposer which allows for greater manufacturability of the packaged integrated circuit parts. Additionally different shaped compressive interposers are described.

Abstract: A semiconductor device has a die (10) overlying and electrically connected to a support structure (11), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects (32, 38) are noise sources to victim interconnects (29, 59) carrying sensitive signals. An arrangement of shield interconnects (51-58) surround the victim interconnect (29, 59) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.

Abstract: A semiconductor device has a die (10) overlying and electrically connected to a support structure (11), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects (32, 38) are noise sources to victim interconnects (29, 59) carrying sensitive signals. An arrangement of shield interconnects (51-58) surround the victim interconnect (29, 59) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.

Abstract: A package substrate (12, 52) has a first surface, a second surface opposite a first surface, and a cavity (22, 70) formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die (20, 60) is placed in the cavity, and a conductive material (24, 72) is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer (28, 78) may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

Abstract: A package substrate (12, 52) has a first surface, a second surface opposite a first surface, and a cavity (22, 70) formed in the first surface that extends into the package substrate. The cavity has a cavity wall substantially perpendicular to the first and second surfaces. An integrated circuit die (20, 60) is placed in the cavity, and a conductive material (24, 72) is placed in the cavity to thermally couple an outer wall of the integrated circuit to the cavity wall. The conductive material improves the heat dissipation path between the integrated circuit die and the package substrate. The cavity may extend through the package substrate to the second surface such that the second surface of the package substrate is substantially coplanar to a surface of the integrated circuit die. An encapsulation layer (28, 78) may be formed over the conductive material, integrated circuit die, and at least a portion of the first surface of the package substrate.

Abstract: A low profile semiconductor device (24) is manufactured by mounting a semiconductor die (26) onto a substrate (28) using an interposer (30). The interposer couples an active surface (32) of the die (26) to conductive traces (33) on the top surface of the substrate. The interposer is directionally conductive so that electrical conductivity is limited to the z-direction through thickness of the interposer. The interposer both affixes the die to the substrate and provides the first level of interconnects for the device. The inactive surface (36) of the die can be exposed for efficient thermal dissipation. An optional heat spreader (50) may be added for increased thermal management. The device may be overmolded, glob-topped, capped, or unencapsulated. Separate die-attach and wire bonding processes are eliminated. A second level of interconnects are provided by either solder balls (38), solder columns (44), or pins (64).

Abstract: The device has a semiconductor die (18) mounted upon a downset X-shape die support (12) of a lead frame (10, 40). The lead frame also has tie bars (16) which are connected to the X-shape die support. Attached to the tie bars are thermal bars (14, 14') which are located between the semiconductor die and inner portion of the leads (20). The inner portion of the leads, the tie bars, and the thermal bars are offset from the plane occupied by the X-shape die support. The thermal bars aid in dissipating the heat from the die into the nearby lead tips so that the heat can be conducted out of the package body (30) through the thermally conductive lead frame. The semiconductor die is wire bonded to the inner portion of the leads. A package body (30) protects the die, the wire bonds (26), the thermal bars, and the inner portion of the leads.

Abstract: A molded semiconductor device (24) having greater resistance to package cracking during board mounting in addition to increased thermal performance is provided wherein the device has a reduced semiconductor die to flag interface and a drop-in heat sink. The semiconductor die (12) is mounted on a leadframe (16) having a flag (15) with an opening to expose a substantial portion of the inactive surface (14) of the die (12). Decreasing the interfacial contact area between the die (12) and the flag (15) reduces the risk of package cracking during board mounting by limiting the area where delamination typically occurs. An encapsulant (22) forms a package body which encompasses an opening (23) to expose a substantial portion of the inactive surface (14) of the semiconductor die (12). A heat sink (26) is inserted into the opening (23), directly coupling the heat sink (26) to the die (12), after the semiconductor package is mounted onto a printed circuit board.

Abstract: A method for making a semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounting surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads are encapsulated in a package body. Also incorporated into the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.

Abstract: A semiconductor device having a heat sink is provided in which an opening through the heat sink enables a vacuum source to be applied to a semiconductor die mounted surface. In one form, a semiconductor die is attached to a mounting surface of a leadframe. The leadframe also has a plurality of leads which are electrically coupled to the semiconductor die. The semiconductor die and portions of the leads encapsulated in a package body. Also incorporated in the package body is a heat sink. The heat sink has an opening which extends through the heat sink and exposes a portion of the mounting surface of the leadframe. The opening is used to apply a vacuum to the mounting surface during the formation of the package body so that the mounting surface and heat sink are held in close proximity. The closeness provides a good thermal conduction path from the semiconductor die to the ambient, thereby enhancing the thermal dissipation properties of the device.