Abstract: Testing capability for an integrated circuit having more than one serializer/deserializer (SERDES) block includes embedding a tester within each block, so that the blocks can be tested independently and concurrently. In one embodiment, a tester includes a functional test controller (FTC) for mode setting and a functional test interface (FTI) for implementing the test procedures. The FTI of each tester is inserted between the SERDES of the same block and core processing logic that is also embedded within the integrated circuit. The FTCs are all interconnected via a test bus that is connected to an input/output controller (IOC) for communication between the testers and an external source, such as a personal computer. Optionally, a built-in-self-tester (BIST) state machine is connected to the test bus.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: Equalization for ports of a crosspoint switch at least partially offsets transmission losses such as skin loss. The equalization may be tailored on a port-by-port basis using adaptive equalization or adjustable equalization, but fixed equalization may be used. In some implementations, each input port or output port of a crosspoint switch has a dedicated equalization circuit that has filtering characteristics that are based on the signal characteristics (e.g., jitter) measured at the affected output port. For an adjustable equalization approach, the adjustable equalization circuitry includes various switched connections that are selectively coupled and decoupled to achieve the target level of equalization.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Abstract: Boundary scan testing methods that detect manufacturing defects in AC-coupled differential pairs may be based on a selected signal parameter: phase or frequency. The data is encoded by the signal parameter. In one embodiment, the signal parameter is compared to reference parameter data provided by the transmitter. In a second embodiment, the reference parameter data is sent from an external source. All the components on board are synchronized with this external source. In a third embodiment, the reference parameter data is embedded in each AC signal between the transmitter and receiver. Two lines of one differential link are used to send different patterns.

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: A parallel automatic synchronization system includes a variable delay devices for receiving and variably delaying N parallel transmitted channel data words over repetitive clock cycles in response to a synchronization latch clock and for synchronously clocking out the parallel data words by a local reference clock (FREF); sync logic devices for receiving repetitive control clocks corresponding to the transmitted channel data words, including a remote recovered clock (FFRM) and the local reference clock (FREF) and for generating the synchronization latch clock which determines the delay position of the variable delay of the delay devices; and output latch devices for clocking out the parallel data words from the variable delay devices with the local reference clock (FREF).

Abstract: A packaged IC includes an IC die with signal and signal complement traces positioned relative to each other to maximize broadside coupling for a matching impedance. The signal and signal complement traces are electrically connected to transmission or receive channels of the IC die. Use of a broadside coupled trace configuration alleviates routing congestion in an IC package and permits an IC to accommodate a greater number of channels within a given surface area than is possible under the prior art.

Abstract: Testing capability for an integrated circuit having more than one serializer/deserializer (SERDES) block includes embedding a tester within each block, so that the blocks can be tested independently and concurrently. In one embodiment, a tester includes a functional test controller (FTC) for mode setting and a functional test interface (FTI) for implementing the test procedures. The FTI of each tester is inserted between the SERDES of the same block and core processing logic that is also embedded within the integrated circuit. The FTCs are all interconnected via a test bus that is connected to an input/output controller (IOC) for communication between the testers and an external source, such as a personal computer. Optionally, a built-in-self-tester (BIST) state machine is connected to the test bus.

Abstract: Equalization for ports of a crosspoint switch at least partially offsets transmission losses such as skin loss. The equalization may be tailored on a port-by-port basis using adaptive equalization or adjustable equalization, but fixed equalization may be used. In some implementations, each input port or output port of a crosspoint switch has a dedicated equalization circuit that has filtering characteristics that are based on the signal characteristics (e.g., jitter) measured at the affected output port. For an adjustable equalization approach, the adjustable equalization circuitry includes various switched connections that are selectively coupled and decoupled to achieve the target level of equalization.

Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Abstract: The present invention provides independent CDR (clock and data recovery) functions on N number of high speed parallel channels, yet only requiring one capacitor. This enables multiple independent CDR channels to be integrated onto one IC with a minimum overhead component of one capacitor. In one embodiment, the present invention provides a multiple channel clock and data recovery system which includes N phase lock loop circuits for receiving in parallel N data channels, each of the N phase lock loop circuits including a digital phase detector and a dual-input VCO in which one VCO input is an analog input for setting the center frequency of the VCO and the other VCO input is a digital input from the respective phase detector for toggling the center frequency and wherein each phase detector compares the phase of the respective incoming data channel with that of the respective VCO output.

Abstract: Boundary scan testing methods that detect manufacturing defects in AC-coupled differential pairs may be based on a selected signal parameter: phase or frequency. The data is encoded by the signal parameter. In one embodiment, the signal parameter is compared to reference parameter data provided by the transmitter. In a second embodiment, the reference parameter data is sent from an external source. All the components on board are synchronized with this external source. In a third embodiment, the reference parameter data is embedded in each AC signal between the transmitter and receiver. Two lines of one differential link are used to send different patterns.

Abstract: A method and system for receiving CIMT encoded data transmitted in simplex mode. The receiver (12) is adapted to receive a stream of digital data and analyze successive portions thereof to identify a predetermined pattern of data. The receiver (12) outputs the received digital data in response to a detection of the predetermined pattern of data and, in the alternative, outputs other data in response to a failure to detect the predetermined pattern of data. In the illustrative embodiment, the stream of digital data is transmitted as conditional invert master transition encoded simplex data. The receiver (12) includes a CIMT decoder (16) which analyzes the input data to identify a master transition therein. The receiver (12) uses a local clock to analyze successive portions of the received data stream and word alignment logic to identify a master transition therein.

Abstract: A dual input voltage controlled oscillator ("VCO") suitable for use in clock and data recovery ("CDR") systems operating at 100s to 1,000s of MB/sec is described. When a PLL using this VCO is locked onto a data stream of a fixed bit rate, the bang/bang frequency of the VCO does not vary due to process and temperature variation occuring either during manufacture or operation. The VCO is also relatively insensitive to supply voltage variations.

Abstract: An integrator includes a capacitor and a bootstrap circuit for detecting any leaking charge from the capacitor and replacing it. The integrator also includes a charge injection circuit for adjusting the charge applied to the capacitor in response to a digital control input to the charge injection circuit. The bootstrap circuit has two transistors to sense leaking charge, and two further transistors forming a differential pair. The bootstrap circuit uses positive feedback and unity gain to replenish the lost charge.

Abstract: An out of lock condition is sensed on a data transition by transition basis in clock recovery apparatus. When an out of lock condition is sensed, a range sweeping signal is generated and summed with the correction signal to sweep the frequency of the clock signal over the frequency range of the VCO. When an out of lock condition is absent, i.e., when the VCO is phase locked, simulated data transitions are generated in the frequency/phase detector. An out of lock condition is sensed by a D flip-flop. Data is coupled to the clock input of the flip-flop, the clock signal is delayed by a fraction of its nominal period and coupled to the D input of the flip-flop. The state of the Q output of the flip-flop indicates an out of lock condition.

Abstract: A method of encoding data for transmission over a communication link. A cumulative polarity of previously-transmitted frames is maintained. A frame is prepared for transmission by combining a data word with a plurality of additional bits. The additional bits provide a master transition. A phantom bit is encoded in the additional bits. If the polarity of the frame is the same as the cumulative polarity, the data bits or in some instances all the bits are inverted so as to maintain balance. Control words and fill words are provided and are distinguished from data words by encoding the additional bits. Control words carry additional data or control instructions and are distinguished from fill words by the number of transitions. The phantom bit either conveys additional data or is used for such purposes as error checking.

Abstract: A method and apparatus for recovering a clock signal from a random NRZ data signal is shown to include a phase detector for detecting the phase difference between the random NRZ data signal and a clock signal and for generating a phase signal representative of the phase difference. The phase signal is a binary signal having first and second logic levels, wherein the first logic level is representative of the clock signal having an early phase relationship with the data signal and wherein the second logic level is representative of the clock signal having a late phase relationship with the data signal. Clock recovery also incorporates an integrator for integrating the phase signal over a period of time and for generating an integration signal representative of such integration and an oscillator for generating the clock signal at a clock frequency responsive to both the phase signal and the integration signal. The clock frequency is determined by a centering factor and an offset factor.