Abstract: The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.

Abstract: An inter-processor synchronization method using point-to-point links, comprises the steps of defining a point-to-point synchronization channel between a source processor and a target processor; executing in the source processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the source processor until the notification is received; executing in the target processor a notification command designed to transmit through the point-to-point link the notification expected by the source processor; executing in the target processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the target processor until the notification is received; and executing in the source processor a notification command designed to transmit through the point-to-point link the notification expected by the target processor.

Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.

Abstract: A circuit for calculating the fused sum of an addend and product of two multiplicands, the addend and multiplicands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplicands are in a lower precision format than the addend, with q>2p, where p and q are respectively the mantissa size of the multiplicand precision format and the addend precision format. The circuit includes a p-bit multiplier receiving the mantissas of the multiplicands; a shift circuit that aligns the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplicands; and an adder that processes q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.

Abstract: A method for determining, by means of a circuit, a result sk+2 of an operation of the type s k + 2 = ( s k ? + • ? a k ) ? + • ? a k + 1 where sk, ak, and ak+1 are fractional signed operands and symbol + • represents a saturating addition operation, comprising: a step of calculation of three sums representative of a possible value of the result, and a step of selection of one of said three sums according to overflows having occurred in the sum calculation. At least one step of the method uses the positive part and the negative part of at least one of the operands.

Abstract: A method for determining, by means of a circuit, a result sk+2 of an operation of the type 1 s k + 2 = ( s k ⁢ + ∘ ⁢ a k ) ⁢ + ∘ ⁢ a k + 1