Abstract: A power converter controller is presented. The controller includes a ramp generator for generating a ramp signal and a ramp adjuster. The ramp adjuster compares a feedback signal of the converter with a threshold signal to obtain a comparison signal, and to adjust an amplitude of the ramp signal based on the comparison signal. Also presented is a constant on time COT power converter including the above controller.

Abstract: A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.

Abstract: A switching converter is presented. The switching converter has a high side power switch coupled to a low side power switch at a switching node, a driver and a timing circuit. The driver generates a drive signal having a on-time to drive the high side power switch. The timing circuit generates a control signal to adjust the on-time during a load transient period.

Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

Abstract: Briefly, embodiments, such as methods, systems and/or circuits for controlling a power signal to be supplied to a processing device. In one aspect, a magnitude of a power supplied to a processing device may be changed based, at least in part on an estimated and/or predicted load.

Abstract: Circuitry comprises driver circuitry to control display of a prevailing display image by display elements of a display device, the driver circuitry generating a signal providing electrical charge for storage by display elements, in which an electrical charge stored by a display element controls a display output of that display element; detector circuitry to detect, for a display image transition from a current display image to a second, display image, a first set of one or more display elements which are in a respective first state controlled by a first stored electrical charge in the current display image and which are required to be in a respective second state controlled by a second electrical charge, in the second display image; switching circuitry, responsive to the detector circuitry, to divert electrical charge from the set of display elements to secondary charge store in response to initiation of the display image transition.

Abstract: Various implementations described herein are related to a device having a power stage that provides an output signal and a first feedback signal based on an input signal and a control signal. The device may have a digital stage with digital circuitry that provides a second feedback signal based on operational activity of the digital circuitry using the output signal. The device may have a control stage that provides the control signal based on the input signal, the first feedback signal and the second feedback signal.

Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

Abstract: In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.

Abstract: In one particular implementation, a circuit includes: a flip flop; and an AND gate, where the circuit is configured to generate edge-triggered set and reset input signals. In another implementation, a method includes: providing, by a digital locked loop (DLL), a plurality of phase outputs; determining, by respective logic circuits, respective pulses to be selected for an output clock corresponding to each of the plurality phase outputs; shifting respective selection windows of the pulses such that each of the selection windows fully overlap the corresponding respective determined pulses; and selecting the pulses.

Abstract: Subject matter disclosed herein may relate to detecting wireless signals and/or signal packets and may relate more particularly to detecting wireless signals and/or signal packets at energy-harvesting devices.

Abstract: In a particular implementation, a method to reduce noise/clock jitter and to generate a “stretched” output clock to optimize for jitter of the output clock is disclosed. The method includes: generating two or more clock phases upon detecting a transient voltage by a detector circuit, generating an output clock signal based on one of the two or more clock phases; and altering a phase speed of the output clock signal to correspond to a phase speed of an input clock signal.

Abstract: Circuitry comprises driver circuitry to control display of a prevailing display image by display elements of a display device, the driver circuitry generating a signal providing electrical charge for storage by display elements, in which an electrical charge stored by a display element controls a display output of that display element; detector circuitry to detect, for a display image transition from a current display image to a second, display image, a first set of one or more display elements which are in a respective first state controlled by a first stored electrical charge in the current display image and which are required to be in a respective second state controlled by a second electrical charge, in the second display image; switching circuitry, responsive to the detector circuitry, to divert electrical charge from the set of display elements to secondary charge store in response to initiation of the display image transition.

Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Various implementations described herein are related to a device. The device may include first circuitry that receives a clock signal and provides one or more phase-shifted pulse signals based on the clock signal. The device may include second circuitry that receives an input voltage, receives the clock signal, and provides an internal control signal based on the input voltage and the clock signal. The device may include third circuitry that receives the internal control signal, receives the one or more phase-shifted pulse signals, and provides an output clock signal based on the internal control signal and the one or more phase-shifted pulse signals.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.

Abstract: Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

Abstract: Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has a step-down converter coupled to an oscillator between a first voltage supply and a second voltage supply. The second stage is coupled to the first stage, and the second stage has a current bias generator coupled to a diode-connected transistor between the first voltage supply and the second voltage supply. The second stage provides an intermediate voltage to the first stage.