Patents by Inventor Benoît Lasbouygues

Benoît Lasbouygues has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Synchronization pulse generator with forced output
    Patent number: 7876141
    Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: January 25, 2011
    Assignees: STMicroelectronics Inc., STMicroelectronics S.A.
    Inventors: Benoît Lasbouygues, Sylvain Clerc, Alain Artieri, Thomas Zounes, Françoise Jacquet
  • PULSE GENERATOR
    Publication number: 20090146720
    Abstract: A generator of synchronization pulses intended for at least two registers, including a first input intended to receive a clock signal and at least one output intended to deliver the pulses on the clock input of said registers, and at least one second input intended to receive a signal for forcing the output, independently from the clock signal, to make said registers transparent.
    Type: Application
    Filed: October 14, 2008
    Publication date: June 11, 2009
    Applicants: STMicroelectronics Inc., STMicroelectronics S.A.
    Inventors: Benoit Lasbouygues, Sylvain Clerc, Alain Artieri, Thomas Zounes, Francoise Jacquet
  • Method and system for evaluating a constraint of a sequential cell
    Patent number: 7487482
    Abstract: The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the ramp of a second signal. The method includes a characterization phase including a first step of determination in which a value of the second ramp is fixed, the value of the first ramp is made to vary so as to determine, a first set of values of the constraint. A second step of determination includes the value of the first ramp being fixed at one of its values taken during the first step of determination, the value of the second ramp is made to vary so as to determine for each value of the second ramp a deviation with respect to the value of the constraint belonging to the first set and corresponding to the fixed value of the first ramp.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: February 3, 2009
    Assignee: STMicroelectronics SA
    Inventors: Benoit Lasbouygues, Joël Schindler
  • METHOD AND SYSTEM FOR EVALUATING A CONSTRAINT OF A SEQUENTIAL CELL
    Publication number: 20060259839
    Abstract: The method evaluates a constraint of a sequential memory cell able to sample an input data item regulated by a clock signal. The constraint is dependent on the ramp of a first signal and on the ramp of a second signal. The method includes a characterization phase including a first step of determination in which a value of the second ramp is fixed, the value of the first ramp is made to vary so as to determine, a first set of values of the constraint. A second step of determination includes the value of the first ramp being fixed at one of its values taken during the first step of determination, the value of the second ramp is made to vary so as to determine for each value of the second ramp a deviation with respect to the value of the constraint belonging to the first set and corresponding to the fixed value of the first ramp.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 16, 2006
    Applicant: STMicroelectronics SA
    Inventors: Benoit Lasbouygues, Joel Schindler