Abstract: A processor including computation groups, each computation group including computation cores, the processor being capable of simultaneously implementing a plurality of applications, each application being implemented by a computation core and possibly requiring a read-mode or write-mode access to an external memory connected to the processor. At least one core, called dedicated core, of at least one computation group is dedicated to management of the external memory, the management making it possible to temporally and spatially organize read-mode and write-mode accesses to the external memory of each application requiring a read or a write in the external memory implemented by the processor.

Abstract: A gateway having an architecture authorizing bidirectional communication between applications located in different domains and presenting a high assurance level of protection. The gateway interconnects a first and second domain. The gateway comprises an internal protocol, first and second protocol adapters hosted within the first and second domains and configured to make a conversion between application data formatted according to an applicative protocol relative to the two domains and gateway data formatted according to the gateway internal protocol, and a security module hosted on a separate platform to communicate with the first and second protocol adapters via first and second data links according to the gateway internal protocol.

Abstract: Multiple-core processor to be connected, by way of communication ports, to a deterministic switched Ethernet network using virtual links to which items of equipment are connected, the processor including clusters each including cores, wherein at least one cluster of the processor implements a switch function that makes it possible to interconnect the items of equipment in the network. At least one cluster of the processor implements an end system function providing functions of sending and receiving data in the network, and at least one cluster of the processor implements an application.

Abstract: Multiple-core processor to be connected, by way of communication ports, to a deterministic switched Ethernet network using virtual links to which items of equipment are connected, the processor including clusters each including cores, wherein at least one cluster of the processor implements a switch function that makes it possible to interconnect the items of equipment in the network. At least one cluster of the processor implements an end system function providing functions of sending and receiving data in the network, and at least one cluster of the processor implements an application.

Abstract: A processor including computation groups, each computation group including computation cores, the processor being capable of simultaneously implementing a plurality of applications, each application being implemented by a computation core and possibly requiring a read-mode or write-mode access to an external memory connected to the processor. At least one core, called dedicated core, of at least one computation group is dedicated to management of the external memory, the management making it possible to temporally and spatially organize read-mode and write-mode accesses to the external memory of each application requiring a read or a write in the external memory implemented by the processor.

Abstract: A gateway having an architecture authorizing bidirectional communication between applications located in different domains and presenting a high assurance level of protection. The gateway interconnects a first and second domain. The gateway comprises an internal protocol, first and second protocol adapters hosted within the first and second domains and configured to make a conversion between application data formatted according to an applicative protocol relative to the two domains and gateway data formatted according to the gateway internal protocol, and a security module hosted on a separate platform to communicate with the first and second protocol adapters via first and second data links according to the gateway internal protocol.

Abstract: A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed.

Abstract: A method and device for loading and executing a plurality of instructions in an avionics system including a processor including at least two cores and a memory controller, each of the cores including a private memory. The plurality of instructions is loaded and executed by execution slots such that, during a first execution slot, a first core has access to the memory controller for transmitting at least one piece of data stored in the private memory thereof and for receiving and storing at least one datum and an instruction from the plurality of instructions in the private memory thereof, while the second core does not have access to the memory controller and executes at least one instruction previously stored in the private memory thereof and such that, during a second execution slot, the roles of the two cores are reversed.