Abstract: A method for manufacturing a quantum electronic circuit includes etching a semiconducting layer so as to obtain: a plurality of pillars; and a qubit layer; oxidising the flank of each pillar; forming coupling rows and coupling columns; and depositing separation layers leaving a contact surface protrude from each pillar.

Abstract: Quantum device formed from a substrate, the substrate being covered: with at least one semiconductor region forming a quantum dot, a detection structure with Coulomb blockade for detecting a state of charge of the quantum dot, said detection structure with Coulomb blockade including a detection island disposed above and facing the quantum dot and able to be coupled to the quantum dot by electrostatic coupling, said detection structure furthermore including at least one first tunnel junction between said detection island and a first gate block, the first gate block being juxtaposed with said detection island.

Abstract: An electronic device including: a support; a semiconductor fin arranged on the support, in which quantum dots are intended to be formed; a plurality of separate first control gates, arranged on the side of a first lateral surface of the fin, one above the other and defining different gate levels, configured to each control the electrostatic potential of one of the quantum dots; at least one second control gate arranged on the side of a second lateral surface of the fin, and configured to control the electrostatic potential of a coupling region between the quantum dots; wherein the second control gate is offset, along a direction perpendicular to the upper surface of the support, with respect to the first control gates.

Abstract: A quantum device, includes a semiconductor portion comprising several first quantum dot regions each disposed between at least two second tunnel barrier regions and placed next to the two second regions; first gates each comprising a first conductive portion; and second gates each comprising at least a second conductive portion and a second dielectric disposed between the second conductive portion and the first conductive portion of one of the first gates, such that each of the first gates is disposed between the semi-conductor portion and one of the second gates. The first and second gates are disposed above the first regions or above the second regions, the second gates being solely located in a vertical extension of the first gates.

Abstract: A quantum device configured to be able to form an array of quantum dots, the device including for this: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; a plurality of fourth gates, each fourth gate being disposed between two second gates along the rows and between two first gates along the columns.

Abstract: A quantum device configured to be able to form an array of quantum dots, the device including for this: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; the active layer including apertures over the entire thickness of the active layer disposed between the rows of the plurality of rows and the columns of the plurality of columns.

Abstract: A method for producing a lateral gate for a semiconductive device, comprising: etching of trenches depositing an electrode laver on the flank of the trenches, and a dielectric material filling. Advantageously, the lateral gate electrostatically controls a distribution of the charge carriers in a metal-oxide-semiconductor (MOS)-type structure, in particular for spin qubit applications.

Abstract: One aspect of the invention relates to an electronic circuit (1) comprising: a semiconductor layer (2), referred to as “qubit layer”; a separation layer (42) extending in contact with the qubit layer (2); first conductive electrodes (61), referred to as “coupling rows”, extending in parallel to the qubit layer (2); second conductive electrodes (62), referred to as “coupling columns”, extending in parallel to the qubit layer (2); third conductive electrodes (71), referred to as “control rows”, extending over the spacer (42); and conductive vias (72), referred to as “control vias”, extending perpendicularly to the face of the qubit layer (2) from the spacer (42) and having one end disposed in proximity to the qubit layer (2).

Abstract: A quantum electronic device comprising: a substrate coated with at least one semiconductor block, insulation zones on either side of the semiconductor block, front gate electrodes on regions of the semiconductor block each forming a quantum dot, one or more exchange electrodes arranged around and at a distance from the semiconductor block, at least one first exchange electrode among the exchange electrodes being provided so as to allow to modulate a tunnel barrier between a first quantum dot and a second quantum dot, this first exchange electrode being formed by a first conductive pad passing through an insulating layer covering the semiconductor block, the insulation zones and the gate electrodes, the first conductive pad having a “lower” end disposed in contact with the first insulation zone.

Abstract: A method is provided for producing a back gate under a semiconductive device surrounded by isolation trenches. The method includes a partial etching of the isolation trenches forming an opening to the sacrificial layer, a selective removal of the sacrificial layer forming a cavity under the device, and a filling of the cavity with a conductive material so as to form the back gate. Advantageously, the formation of the isolation trenches comprises a formation of a sacrificial coating layer at the flanks of the trenches, in contact with the sacrificial layer, before filling with an isolating material, and the partial etching of the trenches comprises a removal of this sacrificial coating layer selectively at the isolating material.

Abstract: An electric transformer comprising a first magnetic circuit coupling a primary coil and a secondary coil, the first magnetic circuit comprising a first limb extending along a vertical axis, the primary coil comprising inner and outer primary coils connected in series, the inner primary coil, the secondary coil, and the outer primary coil being cylindrical and arranged concentrically around the first limb, wherein the inner primary coil, the secondary coil and the outer primary coil are mounted in a manner to maintain a predefined inner gap between the inner primary coil and the secondary coil and a predefined outer gap between the secondary coil and the outer primary coil, the inner and outer gaps being evaluated along a radial direction relative to the vertical axis, the inner and outer gaps increasing a leakage of a magnetic flux between the first coil and the secondary coil.

Abstract: A device including a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

Abstract: An elementary cell for a two-dimensional array of quantum dots, said elementary cell extending along a main plane and including: a plurality of sites occupied by quantum dots capable of confining at least one spin qubit and including at least: a first quantum dot, a second quantum dot adjacent to the first quantum dot in a first direction of the main plane, and a third quantum dot adjacent to the first quantum dot in a second direction of the main plane; and a first blocking site adjacent to the second and third quantum dots, towards which a spin qubit cannot be displaced.

Abstract: A method for fabricating a quantum device includes, in order, forming, on a semiconductor active zone resting on a substrate, a stack having at least one layer of gate material and one or more masking layers on the layer of gate material; forming, facing the active zone, a separation trench by etching through the one or more masking layers, the trench having a bottom revealing the at least one layer of gate material; forming, in the one or more masking layers, one or more pairs of masking blocks, each pair including a second masking block facing a first masking block, the first and second masking blocks being disposed on either side of the trench; and forming, in line with each masking block and by etching the at least one layer of gate material, a gate block so as to form one or more pairs of gate blocks.

Abstract: A method for manufacturing a quantum electronic circuit includes etching a semiconducting layer so as to obtain: a plurality of pillars; and a qubit layer; oxidising the flank of each pillar; forming coupling rows and coupling columns; and depositing separation layers leaving a contact surface protrude from each pillar.

Abstract: A semiconductor device includes a layer of a semiconductor material in which is formed an active zone; a plurality of first gates forming a plurality of lines substantially parallel to each other and covering in part the active zone; a plurality of second gates forming a plurality of columns; at least one third gate, designated measurement gate, extending along an axis substantially parallel to the lines of the plurality of lines and in a direction opposite to the lines of the plurality of lines with respect to the active zone, and a first electrode and a second electrode situated on either side of the plurality of measurement gates in the active zone.

Abstract: An electric transformer comprising a primary coil, a secondary coil and a first magnetic circuit, the first magnetic circuit comprising at least a first limb and a second limb, the primary coil being wound around the first limb of the first magnetic circuit and the secondary coil being wound around the first limb or the second limb of the first magnetic circuit, wherein the electric transformer further comprises a second magnetic circuit acting as a component for setting a total impedance of the electric transformer at a predetermined value, the second magnetic circuit comprising at least a third limb, only one coil among the primary coil and the secondary coil being wound around the third limb of the second magnetic circuit, the second magnetic circuit being independent of the first magnetic circuit.

Abstract: An electric transformer comprising a coil made of at least one winding, the winding being made of a wire comprising a first section, a second section and a middle section between the first and the second sections, the first section forming a first spiral around an axis (Z) and the second section forming a second spiral around the axis, the first and second spirals being located in two separate planes perpendicular to the axis, an inner end of the first spiral, respectively the second spiral, located near the axis being near the middle section of the winding and an outer end of the first spiral, respectively the second spiral, located away from the axis being near a free end of the winding, the first spiral and the second spiral turning around the axis in opposite directions.

Abstract: A device including: a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

Abstract: Quantum device, including: a semiconductor portion comprising several first quantum dot regions each disposed between at least two second tunnel barrier regions and placed next to the two second regions; first gates each comprising a first conductive portion; second gates each comprising at least a second conductive portion and a second dielectric disposed between the second conductive portion and the first conductive portion of one of the first gates, such that each of the first gates is disposed between the semi-conductor portion and one of the second gates; wherein the first and second gates are disposed above the first regions or above the second regions, the second gates being solely located in a vertical extension of the first gates.