Abstract: An electronic circuit including a bus (3521), a peripheral (3510.i/3552.1) coupled to the bus (3521), the peripheral having a storing circuit (3620.i, 3625.i) for a succession-presetting and a parameter setting currently-effective for peripheral operation on the bus (3521); and a power management circuit (3570) operable in response to a power management transition request (GO_bit) to send a first signal (START_bit_i) to the peripheral, and to initiate a bus frequency transition, and to send a second signal (PER_ENABLE_i) to the peripheral after the bus frequency transition; and the peripheral is responsive to the first signal (START_bit_i) to stall peripheral operation on the bus (3521), the peripheral operable to automatically promote the succession pre-setting to currently-effective status for the peripheral after peripheral operations on the bus (3521) are stalled and responsive to the second signal (PER_ENABLE_i) to re-enable peripheral operation on the bus (3521).

Abstract: An electronic circuit including a bus (3521), a peripheral (3510.i/3552.1) coupled to the bus (3521), the peripheral having a storing circuit (3620.i, 3625.i) for a succession-presetting and a parameter setting currently-effective for peripheral operation on the bus (3521); and a power management circuit (3570) operable in response to a power management transition request (GO_bit) to send a first signal (START_bit_i) to the peripheral, and to initiate a bus frequency transition, and to send a second signal (PER_ENABLE_i) to the peripheral after the bus frequency transition; and the peripheral is responsive to the first signal (START_bit_i) to stall peripheral operation on the bus (3521), the peripheral operable to automatically promote the succession pre-setting to currently-effective status for the peripheral after peripheral operations on the bus (3521) are stalled and responsive to the second signal (PER_ENABLE_i) to re-enable peripheral operation on the bus (3521).

Abstract: A system comprising a FIFO data buffer having a programmable threshold level, which is initially set to a worst case scenario level, so that the FIFO data buffer does not empty of data. The system also comprises a hardware device which is configured to adjust the threshold level in the FIFO data buffer to a level equal to the current threshold level minus the amount of remaining data in the FIFO data buffer at the time new data enters the FIFO data buffer. The hardware device is also configured to adjust the threshold level to the initial threshold level if the FIFO data buffer underflows. The hardware device may be coupled to the FIFO data buffer, implemented in the FIFO data buffer, or implemented in the display subsystem. The system may be implemented in a mobile communications device.