Patents by Inventor Benoit de Lescure

Benoit de Lescure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289384
    Abstract: In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) interconnect used in a system-on-chip (SoC).
    Type: Grant
    Filed: February 6, 2022
    Date of Patent: April 29, 2025
    Assignee: ARTERIS, INC.
    Inventors: K. Charles Janac, Vincent Thibaut, Benoit de Lescure
  • Patent number: 12237980
    Abstract: Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 25, 2025
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit De Lescure, Xavier Van Ruymbeke
  • Patent number: 12204833
    Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: January 21, 2025
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit De Lescure
  • Patent number: 12184499
    Abstract: A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: December 31, 2024
    Assignee: ARTERIS, INC.
    Inventor: Benoit de Lescure
  • Patent number: 12135928
    Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: November 5, 2024
    Assignee: ARTERIS, INC.
    Inventors: Benoit de Lescure, Moez Cherif
  • Patent number: 12067335
    Abstract: Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: August 20, 2024
    Assignee: ARTERIS, INC.
    Inventors: Mokhtar Hirech, Benoit de Lescure
  • Patent number: 12038866
    Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: July 16, 2024
    Assignee: ARTERIS, INC.
    Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
  • Patent number: 11956127
    Abstract: An initial Network on Chip (NoC) topology based on a set of initial requirements is incrementally modified to satisfy a set of different requirements. Each incremental modification includes minimizing a number of changes to existing components in the initial topology. Minimizing the changes includes preserving names of the existing components in the initial NoC topology.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: April 9, 2024
    Assignee: ARTERIS, INC.
    Inventors: Benoit de Lescure, Moez Cherif
  • Patent number: 11836427
    Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: December 5, 2023
    Assignee: ARTERIS, INC.
    Inventors: Benoit De Lescure, Moez Cherif
  • Patent number: 11831557
    Abstract: A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: November 28, 2023
    Assignee: ARTERIS, INC.
    Inventors: John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande
  • Patent number: 11784909
    Abstract: Qualifying networks properties that can be used for topology generation of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metrics are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to determine if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wire length used by the network.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: October 10, 2023
    Assignee: ARTERIS, INC.
    Inventors: Benoit de Lescure, Moez Cherif
  • Patent number: 11748535
    Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: September 5, 2023
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit De Lescure
  • Patent number: 11665776
    Abstract: System and methods are disclosed for transformation of a network, such as a network-on-chip (NoC). The system applies a method of clustering to nodes and edges. The clustering transforms the network and produces a deadlock free and (near-)optimal network that honors the constraints of the input network's floorplan and specification.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: May 30, 2023
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit de Lescure
  • Patent number: 11657203
    Abstract: A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC. The process takes a set of constraints as inputs and produces a NoC with all its elements configured and a placement of such elements on the floorplan of the chip.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 23, 2023
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit de Lescure
  • Patent number: 11601357
    Abstract: System and methods are disclosed to qualify networks properties and that can be used for topology synthesis of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metric are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to understand if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wore length used by the network.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: March 7, 2023
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit de Lescure
  • Patent number: 11558259
    Abstract: A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC). The roadmap includes a set of possible positions for placement of edges and nodes, which are known to be an acceptable and good position for placement of these network elements, that honors the constraints of the network. These known positions are made available to the system for synthesis of the network and generating the connectivity and placement based on the physical roadmap.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 17, 2023
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit de Lescure
  • Patent number: 11449655
    Abstract: Systems and methods are disclosed that implement a tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically determine data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: September 20, 2022
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit De Lescure
  • Patent number: 11436185
    Abstract: Systems and methods are disclosed for broadcasting transactions, inside a network-on-chip (NoC), from a master to multiple slaves and for receiving responses. The transactions originate from a master and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the master. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple slaves. The slaves send a response, which is transported back by the NoC to the corresponding master.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: September 6, 2022
    Assignee: ARTERIS, INC.
    Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
  • Patent number: 11416352
    Abstract: A distributed system implementation for cache coherence comprises distinct agent interface units, coherency controllers, and memory interface units. The agents send requests in the form of read and write transactions. The system also includes a memory that includes coherent memory regions. The memory is in communication with the agents. The system includes a coherent interconnect in communication with the memory and the agents. The system includes a second identical coherent interconnect in communication with the memory and the agents. The system also includes a comparator for comparing at least two inputs, the comparator is in communication with the two coherent interconnects.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 16, 2022
    Assignee: ARTERIS, INC.
    Inventors: Jean Philippe Loison, Benoit de Lescure, Alexis Boutiller, Rohit Bansal, Parimal Gaikwad, Mohammed Khaleeluddin
  • Patent number: 11368402
    Abstract: A system and method for soft locking on an ingress port of a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port is given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts, which can make forward progress in the network, are not available, the networking device may choose another port. The system transmits packet parts from the other port until the soft locked port has packet parts available that can make forward progress in the network. Any arbitration scheme may be used to select the port that is soft locked and to select the other ports to transmit from when the soft locked port does not have packet parts that can make forward progress in the network. Once the packet (or all the packet parts) on the soft locked port has completed transmission, the soft lock of the soft locked port is released.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: June 21, 2022
    Assignee: ARTERIS, INC.
    Inventors: John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande