Abstract: Failure mode, effects, and diagnostic analysis (FMEDA) is performed on hardware Intellectual Property (IP) of an electronic system. The analysis includes accessing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model; and compiling the safety library components and the hardware IP. The compiling includes mapping instances of hardware models in the hardware IP to corresponding safety library components and aggregating the characterizations and safety data of the corresponding components.

Abstract: A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.

Abstract: A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements' position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.

Abstract: A tool makes modifications to the chip floorplan and the network-on-chip (NoC) elements' position on the floorplan and updates the number and position of the pipeline elements in a pipeline stage automatically, resulting in fewer errors and higher productivity.

Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.

Abstract: Design of a network-on-chip (NoC) includes searching for a potential deadlock in a topology of the NoC, where the potential deadlock is caused by an external dependency in which input of data into the NoC is dependent on output of data from the NoC. The NoC design further includes modifying the NoC topology to resolve the potential deadlock.

Abstract: Design of a network-on-chip (NoC) includes searching for a potential deadlock in a topology of the NoC, where the potential deadlock is caused by an external dependency in which input of data into the NoC is dependent on output of data from the NoC. The NoC design further includes modifying the NoC topology to resolve the potential deadlock.

Abstract: An existing network-on-chip (NoC) topology that is derived based on a set of initial requirements is changed using incremental modifications that satisfy a set of updated requirements. Each incremental modification includes minimizing the number of changes to existing components in the existing NoC topology. Minimizing the changes includes preserving names of the existing components in the existing NoC topology and removing existing components or connections as well as adding in new component and new connections.

Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.

Abstract: Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.

Abstract: System and methods are disclosed for aggregating identical requests sent to a target from multiple initiators through a network-on-chip (NoC). The requests are marked for aggregation. The NoC uses request aggregators (RA) as an aggregation point to aggregate the identical requests that are marked for aggregation. At the aggregation point, the identical requests are reduced to a single request. The single request is sent to the target. The process is repeated in a cascaded fashion through the NoC, possibly involving multiple request aggregators. When a response transaction is received back from the target, which is at the aggregation point closest to the target, the response transaction is duplicated and sent to every original requester, either directly or through other request aggregators, which further duplicate the already duplicated response transaction.

Abstract: System and methods are disclosed for aggregating requests sent from multiple initiators to the same target through a network-on-chip (NoC). The requests are marked for aggregation. The NoC uses request aggregators (RA) as an aggregation point to aggregate the identical requests that are marked for aggregation. At the aggregation point, the identical requests are reduced to a single request. The single request is sent to the target. The process is repeated in a cascaded fashion through the NoC, possibly involving multiple request aggregators. When a response transaction is received back from the target, which is at the aggregation point closest to the target, the response transaction is duplicated and sent to every original requester, either directly or through other request aggregators, which further duplicate the already duplicated response transaction.

Abstract: In accordance with the various aspects and embodiment of the invention, a design tool is disclosed that automates the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocols for the IP blocks and the network-on-chip (NoC). One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the NoC used in a system-on-chip (SoC).

Abstract: Design of a network-on-chip (NoC) includes searching for a potential deadlock in a topology of the NoC, where the potential deadlock is caused by an external dependency in which input of data into the NoC is dependent on output of data from the NoC. The NoC design further includes modifying the NoC topology to resolve the potential deadlock.

Abstract: An initial Network on Chip (NoC) topology based on a set of initial requirements is incrementally modified to satisfy a set of different requirements. Each incremental modification includes minimizing a number of changes to existing components in the initial topology. Minimizing the changes includes preserving names of the existing components in the initial NoC topology.

Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a design tool is used to synthesize and generate the NoC from a set of constraints. The tool takes minimum changes to the NoC and produces consistent results between different synthesis runs, which have slight varying constraints.

Abstract: In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) interconnect used in a system-on-chip (SoC).

Abstract: Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.

Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.

Abstract: A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.