Patents by Inventor Benoit de Lescure

Benoit de Lescure has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289384
    Abstract: In accordance with the various aspects and embodiment of the invention, a system and method are disclosed that automate the process of generating protocol converters using machine-readable descriptions of the external hardware components interfaces and the associated protocol. One advantage of the invention is lowered mistakes in generating the protocol converters. Another advantage is increased productivity when designing the interconnect, such as a network-on-chip (NoC) interconnect used in a system-on-chip (SoC).
    Type: Grant
    Filed: February 6, 2022
    Date of Patent: April 29, 2025
    Assignee: ARTERIS, INC.
    Inventors: K. Charles Janac, Vincent Thibaut, Benoit de Lescure
  • Patent number: 12237980
    Abstract: Systems and methods are disclosed for synthesis of a network, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC description from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting network description output includes placement of elements on a floorplan of a chip that represents the network, such as the NoC.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: February 25, 2025
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit De Lescure, Xavier Van Ruymbeke
  • Patent number: 12204833
    Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
    Type: Grant
    Filed: September 5, 2023
    Date of Patent: January 21, 2025
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit De Lescure
  • Patent number: 12184499
    Abstract: A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: December 31, 2024
    Assignee: ARTERIS, INC.
    Inventor: Benoit de Lescure
  • Publication number: 20240411969
    Abstract: Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.
    Type: Application
    Filed: August 19, 2024
    Publication date: December 12, 2024
    Applicant: ARTERIS, INC.
    Inventors: Mokhtar HIRECH, Benoit de LESCURE
  • Publication number: 20240378174
    Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 14, 2024
    Applicant: ARTERIS, INC.
    Inventors: SYED IJLAL ALI SHAH, John CODDINGTON, Benoit De LESCURE
  • Patent number: 12135928
    Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
    Type: Grant
    Filed: December 5, 2023
    Date of Patent: November 5, 2024
    Assignee: ARTERIS, INC.
    Inventors: Benoit de Lescure, Moez Cherif
  • Patent number: 12067335
    Abstract: Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: August 20, 2024
    Assignee: ARTERIS, INC.
    Inventors: Mokhtar Hirech, Benoit de Lescure
  • Publication number: 20240259274
    Abstract: An initial Network on Chip (NoC) topology based on a set of initial requirements is incrementally modified to satisfy a set of different requirements. Each incremental modification includes minimizing a number of changes to existing components in the initial topology. Minimizing the changes includes preserving names of the existing components in the initial NoC topology.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Applicant: ARTERIS, INC.
    Inventors: Benoit de LESCURE, Moez CHERIF
  • Patent number: 12038866
    Abstract: A broadcast adapter in a network-on-chip (NoC) is used for broadcasting transactions in the form of packets from an initiator to multiple targets and for receiving responses from the targets that are combined and sent to the initiator. The transactions originate from an initiator and are send, using the NoC, to broadcast adapters using a special range of addresses. The broadcast adapters receive the transactions from the initiator. The broadcast adapters duplicate the transactions and send the duplicated transaction to multiple targets. The targets send a response, which is transported back by the NoC to the corresponding initiator.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: July 16, 2024
    Assignee: ARTERIS, INC.
    Inventors: Syed Ijlal Ali Shah, John Coddington, Benoit de Lescure
  • Publication number: 20240220692
    Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
    Type: Application
    Filed: December 5, 2023
    Publication date: July 4, 2024
    Applicant: ARTERIS, INC.
    Inventors: Benoit de LESCURE, Moez CHERIF
  • Publication number: 20240211666
    Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
    Type: Application
    Filed: September 5, 2023
    Publication date: June 27, 2024
    Applicant: ARTERIS, INC.
    Inventors: Moez CHERIF, Benoit De LESCURE
  • Patent number: 11956127
    Abstract: An initial Network on Chip (NoC) topology based on a set of initial requirements is incrementally modified to satisfy a set of different requirements. Each incremental modification includes minimizing a number of changes to existing components in the initial topology. Minimizing the changes includes preserving names of the existing components in the initial NoC topology.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: April 9, 2024
    Assignee: ARTERIS, INC.
    Inventors: Benoit de Lescure, Moez Cherif
  • Patent number: 11836427
    Abstract: A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: December 5, 2023
    Assignee: ARTERIS, INC.
    Inventors: Benoit De Lescure, Moez Cherif
  • Patent number: 11831557
    Abstract: A system and method for soft locking for a networking device in a network, such as a network-on-chip (NoC). Once a soft lock is established, the port and packet are given transmitting priority so long has the port has an available packet or packet parts that can make forward progress in the network. When the soft lock port's packet parts are not available, the networking device may choose another port and/or another packet. Any arbitration scheme may be used. Once the packet (or all the packet parts) has completed transmission, the soft lock is released.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: November 28, 2023
    Assignee: ARTERIS, INC.
    Inventors: John Coddington, Benoit de Lescure, Syed Ijlal Ali Shah, Sanjay Despande
  • Publication number: 20230342538
    Abstract: Failure mode, effects, and diagnostic analysis (FMEDA) is performed on hardware Intellectual Property (IP) of an electronic system. The analysis includes accessing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model; and compiling the safety library components and the hardware IP. The compiling includes mapping instances of hardware models in the hardware IP to corresponding safety library components and aggregating the characterizations and safety data of the corresponding components.
    Type: Application
    Filed: April 16, 2023
    Publication date: October 26, 2023
    Applicant: ARTERIS, INC.
    Inventors: Stefano LORENZINI, Benoit de LESCURE
  • Publication number: 20230325566
    Abstract: Generation of a full register-transfer level (RTL) description of an electronics system includes generating an optimized pipeline configuration from inputs including a database of RTL elements, and a list of configurable pipeline components; and generating the full RTL description with the pipeline components configured according to the optimized pipeline configuration. Generating the configuration includes performing a search for a configuration that optimizes area and timing.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Applicant: ARTERIS, INC.
    Inventors: Mokhtar HIRECH, Benoit de LESCURE
  • Patent number: 11784909
    Abstract: Qualifying networks properties that can be used for topology generation of networks, such as a network-on-chip (NoC). In accordance with various embodiments and different aspects of the invention, quality metrics are generated, analyzed, and used to determine a quantitative quality set of values for a given generated solution for a network. The method disclosed allows the network designer or an automated network generation process to determine if the results produced are a good, an average or a bad solution. The advantage of the invention includes simplification of design process and the work of the designer by using quality metrics. Various quality metrics are generated using network definitions. These quality metrics provide quality evaluation and the quality assessment of the optimization process for a generated (optimized) network. The quality metrics include analyzing latency through a network and analyzing total wire length used by the network.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: October 10, 2023
    Assignee: ARTERIS, INC.
    Inventors: Benoit de Lescure, Moez Cherif
  • Patent number: 11748535
    Abstract: Systems and methods are disclosed synthesis of network, such as a network-on-chip (NoC). The network is initially synthesized. In accordance with various embodiments and aspects of the invention, a tool is used to synthesize and generate the NoC from a set of constraints. The tool produces consistent results between different synthesis runs, which have slight varying constraints.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: September 5, 2023
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit De Lescure
  • Patent number: 11665776
    Abstract: System and methods are disclosed for transformation of a network, such as a network-on-chip (NoC). The system applies a method of clustering to nodes and edges. The clustering transforms the network and produces a deadlock free and (near-)optimal network that honors the constraints of the input network's floorplan and specification.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: May 30, 2023
    Assignee: ARTERIS, INC.
    Inventors: Moez Cherif, Benoit de Lescure