Patents by Inventor Benoit Dupont
Benoit Dupont has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315472Abstract: A processor core including an N-bit system memory interface; a register file comprising a plurality of general purpose registers of capacity less than N bits; a set of N-bit vector registers ; in its instruction set, a register manipulation instruction executable with the following parameters: a) a value defining in the set of vector registers a buffer area formed by a plurality of consecutive vector registers, and b) a reference to a first general purpose register , the first general purpose register containing an index identifying a vector register within the buffer area; and an execution unit configured to, upon execution of a register manipulation instruction, read or write, in one cycle, N bits in a vector register identified from the value defining the buffer area and the index contained in the first general purpose register).Type: ApplicationFiled: March 30, 2023Publication date: October 5, 2023Inventor: Benoit Dupont de Dinechin
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Patent number: 11604646Abstract: A method of processing data by a processor, the method comprising the steps of: receiving, by the processor, an instruction including an operator code associated with three register references designating registers configured to contain pairs of multiplication operands, an addition operand, and a result register configured to receive an operator result, the operator code designating an operator configured to compute products of the pairs of multiplication operands and add the products with the addition operand; decoding the instruction by an instruction decoder of the processor, to determine the operator to be executed, and the registers containing the operands to be supplied to the operator and the result of the operator; actuating the operator by an arithmetic circuit of the processor, consuming the operands in the registers designated by the register references; and storing the result of the operator in the designated result register.Type: GrantFiled: December 29, 2021Date of Patent: March 14, 2023Assignee: KalrayInventor: Benoit Dupont de Dinechin
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Publication number: 20220222073Abstract: A method of processing data by a processor, the method comprising the steps of: receiving, by the processor, an instruction including an operator code associated with three register references designating registers configured to contain pairs of multiplication operands, an addition operand, and a result register configured to receive an operator result, the operator code designating an operator configured to compute products of the pairs of multiplication operands and add the products with the addition operand; decoding the instruction by an instruction decoder of the processor, to determine the operator to be executed, and the registers containing the operands to be supplied to the operator and the result of the operator; actuating the operator by an arithmetic circuit of the processor, consuming the operands in the registers designated by the register references; and storing the result of the operator in the designated result register.Type: ApplicationFiled: December 29, 2021Publication date: July 14, 2022Inventor: Benoit Dupont de Dinechin
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Publication number: 20220207108Abstract: A method is disclosed for block processing two matrices stored in a same shared memory, one being stored by rows and the other being stored by columns, using a plurality of processing elements (PE), where each processing element is connected to the shared memory by a respective N-bit access and to a first adjacent processing element by a bidirectional N-bit point-to-point link. The method comprising the following steps carried out in one processor instruction cycle: receiving in the processing elements respective different N-bit segments of a same one of the two matrices by the respective memory accesses; and exchanging with the first adjacent processing element, by means of the point-to-point link, N-bit segments of a first of the two matrices which were received in the adjacent processing elements in a previous instruction cycle.Type: ApplicationFiled: December 30, 2021Publication date: June 30, 2022Inventors: Benoit Dupont de Dinechin, Julien Le Maire, Nicolas Brunie
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Patent number: 11169808Abstract: The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.Type: GrantFiled: December 20, 2019Date of Patent: November 9, 2021Assignee: KalrayInventors: Benoit Dupont de Dinechin, Julien Le Maire, Nicolas Brunie
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Patent number: 11144480Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.Type: GrantFiled: March 7, 2017Date of Patent: October 12, 2021Assignee: KALRAYInventors: Benoit Dupont De Dinechin, Marta Rybczynska, Vincent Ray
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Publication number: 20210200904Abstract: A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.Type: ApplicationFiled: December 31, 2020Publication date: July 1, 2021Inventors: Pierre GUIRONNET DE MASSAS, Vincent RAY, Benoit DUPONT DE DINECHIN
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Patent number: 10915488Abstract: An inter-processor synchronization method using point-to-point links, comprises the steps of defining a point-to-point synchronization channel between a source processor and a target processor; executing in the source processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the source processor until the notification is received; executing in the target processor a notification command designed to transmit through the point-to-point link the notification expected by the source processor; executing in the target processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the target processor until the notification is received; and executing in the source processor a notification command designed to transmit through the point-to-point link the notification expected by the target processor.Type: GrantFiled: May 19, 2015Date of Patent: February 9, 2021Assignee: KALRAYInventors: Benoît Dupont De Dinechin, Vincent Ray
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Publication number: 20200210248Abstract: The disclosure relates to an interprocessor synchronization system, comprising a plurality of processors; a plurality of unidirectional notification lines connecting the processors in a chain; in each processor: a synchronization register having bits respectively associated with the notification lines, connected to record the respective states of upstream notification lines, propagated by an upstream processor, and a gate controlled by a configuration register to propagate the states of the upstream notification lines on downstream notification lines to a downstream processor.Type: ApplicationFiled: December 27, 2019Publication date: July 2, 2020Inventors: Benoit Dupont de Dinechin, Arnaud Odinot, Vincent Ray
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Publication number: 20200201642Abstract: The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.Type: ApplicationFiled: December 20, 2019Publication date: June 25, 2020Inventors: Benoit Dupont de Dinechin, Julien Le Maire, Nicolas Brunie
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Patent number: 10250697Abstract: A token bucket flow rate limiter is provided for a data transmission, comprising a token counter configured to be incremented at a rate determining the average flow rate of the transmission; a frequency divider connected to control incrementing of the token counter from a clock, the divider having an integer division factor; and a modulator configured to alternate the division factor between two different integers so as to make the resulting average flow rate tend to a programmed flow rate comprised between two boundary flow rates respectively corresponding to the two integers.Type: GrantFiled: November 18, 2016Date of Patent: April 2, 2019Assignee: KALRAYInventors: Duco Van Amstel, Alexandre Blampey, Benoit Dupont De Dinechin
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Patent number: 10175989Abstract: A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.Type: GrantFiled: April 27, 2015Date of Patent: January 8, 2019Assignee: KALRAYInventors: Renaud Ayrignac, Vincent Ray, Benoît Dupont De Dinechin
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Patent number: 9898251Abstract: The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.Type: GrantFiled: May 19, 2015Date of Patent: February 20, 2018Assignee: KALRAYInventors: Benoît Dupont De Dinechin, Marta Rybczynska
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Patent number: 9780138Abstract: A method and device of driving a radiation sensor pixel is disclosed. The sensor pixel comprises a sensing element capable of charge generation as a response to impinging radiation, a floating diffusion node, a transfer gate between the sensing element and the floating diffusion node, and a charge storage device connected to the floating diffusion node via a switch. The method comprises biasing the transfer gate to three or more bias voltages OFF, ON and an intermediate bias between OFF and ON. During the period in which the transfer gate is biased to the intermediate bias, if the sensor reaches saturation, the overflown charges may be collected and part of them stored in the charge storage device, for further analysis and merging.Type: GrantFiled: November 26, 2014Date of Patent: October 3, 2017Assignee: CAELESTE CVBAInventor: Benoit Dupont
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Patent number: 9766951Abstract: A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.Type: GrantFiled: May 26, 2015Date of Patent: September 19, 2017Assignee: KALRAYInventors: Thomas Champseix, Benoît Dupont De Dinechin, Pierre Guironnet De Massas
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Publication number: 20170255571Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.Type: ApplicationFiled: March 7, 2017Publication date: September 7, 2017Applicant: KALRAYInventors: Benoit DUPONT DE DINECHIN, Marta RYBCZYNSKA, Vincent RAY
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Publication number: 20170192792Abstract: A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.Type: ApplicationFiled: April 27, 2015Publication date: July 6, 2017Applicant: KALRAYInventors: Renaud AYRIGNAC, Vincent RAY, Benoît DUPONT DE DINECHIN
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Publication number: 20170149908Abstract: A token bucket flow rate limiter is provided for a data transmission, comprising a token counter configured to be incremented at a rate determining the average flow rate of the transmission; a frequency divider connected to control incrementing of the token counter from a clock, the divider having an integer division factor; and a modulator configured to alternate the division factor between two different integers so as to make the resulting average flow rate tend to a programmed flow rate comprised between two boundary flow rates respectively corresponding to the two integers.Type: ApplicationFiled: November 18, 2016Publication date: May 25, 2017Inventors: Duco VAN AMSTEL, Alexandre BLAMPEY, Benoit DUPONT DE DINECHIN
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Patent number: 9565122Abstract: A credit-based data flow control method between a consumer device and a producer device. The method includes the steps of decrementing a credit counter for each transmission of a sequence of data by the producer device, arresting data transmission when the credit counter reaches zero, sending a credit each time the consumer device has consumed a data sequence and incrementing the credit counter upon receipt of each credit.Type: GrantFiled: October 9, 2012Date of Patent: February 7, 2017Assignee: KALRAYInventors: Michel Harrand, Yves Durand, Patrice Couvert, Thomas Champseix, Benoît Dupont De Dinechin
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Patent number: 9367287Abstract: A circuit for calculating the fused sum of an addend and product of two multiplication operands, the addend and multiplication operands being binary floating-point numbers represented in a standardized format as a mantissa and an exponent is provided. The multiplication operands are in a lower precision format than the addend, with q>2p, where p and q are the mantissa size of the multiplication operand and addend precision formats. The circuit includes a p-bit multiplier receiving the mantissas of the multiplication operands; a shift circuit aligning the mantissa of the addend with the product output by the multiplier based on the exponent values of the addend and multiplication operands; and an adder processing q-bit mantissas, receiving the aligned mantissa of the addend and the product, the input lines of the adder corresponding to the product being completed to the right by lines at 0 to form a q-bit mantissa.Type: GrantFiled: April 19, 2012Date of Patent: June 14, 2016Assignee: KALRAYInventors: Florent Dupont De Dinechin, Nicolas Brunie, Benoit Dupont De Dinechin