Abstract: A hardware operator configured to add N+1 operands defined in a floating point format comprising a mantissa and an exponent, the operator comprising a sorting circuit configured to sort the operands in decreasing order of exponent, producing a sorted sequence of operands; an adder having N+1 compacted inputs, each compacted input having a width of at most N+1 consecutive bitfields, each bitfield having a width equal to a mantissa width plus a respective margin of bits; a shifter for each operand of the sorted sequence, configured to shift the mantissa of the operand by a respective right shift value on the corresponding compacted input of the adder; and a shift calculation circuit configured to calculate the right shift values so that the mantissas are positioned in corresponding bitfields of the adder inputs according to differences between the exponents. The shift calculation circuit is configured as a parallel prefix tree.

Abstract: The present disclosure relates to a hardware hybrid multiply-accumulate operator configured to multiply a multiplicand formatted as a floating-point number by a multiplicand formatted as an integer and add an integer-formatted result of the multiplication to an operand formatted as an integer.

Abstract: The disclosure relates to an interprocessor synchronization system, comprising a plurality of processors; a plurality of unidirectional notification lines connecting the processors in a chain; in each processor: a synchronization register having bits respectively associated with the notification lines, connected to record the respective states of upstream notification lines, propagated by an upstream processor, and a gate controlled by a configuration register to propagate the states of the upstream notification lines on downstream notification lines to a downstream processor.

Abstract: A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.

Abstract: A processor core including an N-bit system memory interface; a register file comprising a plurality of general purpose registers of capacity less than N bits; a set of N-bit vector registers ; in its instruction set, a register manipulation instruction executable with the following parameters: a) a value defining in the set of vector registers a buffer area formed by a plurality of consecutive vector registers, and b) a reference to a first general purpose register , the first general purpose register containing an index identifying a vector register within the buffer area; and an execution unit configured to, upon execution of a register manipulation instruction, read or write, in one cycle, N bits in a vector register identified from the value defining the buffer area and the index contained in the first general purpose register).

Abstract: A method of processing data by a processor, the method comprising the steps of: receiving, by the processor, an instruction including an operator code associated with three register references designating registers configured to contain pairs of multiplication operands, an addition operand, and a result register configured to receive an operator result, the operator code designating an operator configured to compute products of the pairs of multiplication operands and add the products with the addition operand; decoding the instruction by an instruction decoder of the processor, to determine the operator to be executed, and the registers containing the operands to be supplied to the operator and the result of the operator; actuating the operator by an arithmetic circuit of the processor, consuming the operands in the registers designated by the register references; and storing the result of the operator in the designated result register.

Abstract: A method of processing data by a processor, the method comprising the steps of: receiving, by the processor, an instruction including an operator code associated with three register references designating registers configured to contain pairs of multiplication operands, an addition operand, and a result register configured to receive an operator result, the operator code designating an operator configured to compute products of the pairs of multiplication operands and add the products with the addition operand; decoding the instruction by an instruction decoder of the processor, to determine the operator to be executed, and the registers containing the operands to be supplied to the operator and the result of the operator; actuating the operator by an arithmetic circuit of the processor, consuming the operands in the registers designated by the register references; and storing the result of the operator in the designated result register.

Abstract: A method is disclosed for block processing two matrices stored in a same shared memory, one being stored by rows and the other being stored by columns, using a plurality of processing elements (PE), where each processing element is connected to the shared memory by a respective N-bit access and to a first adjacent processing element by a bidirectional N-bit point-to-point link. The method comprising the following steps carried out in one processor instruction cycle: receiving in the processing elements respective different N-bit segments of a same one of the two matrices by the respective memory accesses; and exchanging with the first adjacent processing element, by means of the point-to-point link, N-bit segments of a first of the two matrices which were received in the adjacent processing elements in a previous instruction cycle.

Abstract: The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.

Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.

Abstract: A processor having a plurality of protection rings and comprising a protection ring management system in which the attributions of exceptions or privileged resources to protection rings are defined by a programmable table.

Abstract: An inter-processor synchronization method using point-to-point links, comprises the steps of defining a point-to-point synchronization channel between a source processor and a target processor; executing in the source processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the source processor until the notification is received; executing in the target processor a notification command designed to transmit through the point-to-point link the notification expected by the source processor; executing in the target processor a wait command expecting a notification associated with the synchronization channel, wherein the wait command is designed to stop the target processor until the notification is received; and executing in the source processor a notification command designed to transmit through the point-to-point link the notification expected by the target processor.

Abstract: The disclosure relates to an interprocessor synchronization system, comprising a plurality of processors; a plurality of unidirectional notification lines connecting the processors in a chain; in each processor: a synchronization register having bits respectively associated with the notification lines, connected to record the respective states of upstream notification lines, propagated by an upstream processor, and a gate controlled by a configuration register to propagate the states of the upstream notification lines on downstream notification lines to a downstream processor.

Abstract: The disclosure relates to a processor including an N-bit data bus configured to access a memory; a central processing unit CPU connected to the data bus; a coprocessor coupled to the CPU, including a register file with N-bit registers; an instruction processing unit in the CPU, configured to, in response to a load-scatter machine instruction received by the CPU, read accessing a memory address and delegating to the coprocessor the processing of the corresponding N-bit word presented on the data bus; and a register control unit in the coprocessor, configured by the CPU in response to the load-scatter instruction, to divide the word presented on the data bus into K segments and writing the K segments at the same position in K respective registers, the position and the registers being designated by the load-scatter instruction.

Abstract: A token bucket flow rate limiter is provided for a data transmission, comprising a token counter configured to be incremented at a rate determining the average flow rate of the transmission; a frequency divider connected to control incrementing of the token counter from a clock, the divider having an integer division factor; and a modulator configured to alternate the division factor between two different integers so as to make the resulting average flow rate tend to a programmed flow rate comprised between two boundary flow rates respectively corresponding to the two integers.

Abstract: A processor including multiple processing units for processing multiple elementary instructions in parallel, the elementary instructions including one or more syllables, each having a rank in the elementary instruction, and an input circuit configured to receive an instruction bundle including multiple elementary instructions, and to transmit to the processing units all syllables of first rank of the elementary instructions of the instruction bundle before syllables of second rank of the elementary instructions of the instruction bundle, the syllables of same rank being ordered according to the target processing unit of each syllable.

Abstract: The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.

Abstract: A method and device of driving a radiation sensor pixel is disclosed. The sensor pixel comprises a sensing element capable of charge generation as a response to impinging radiation, a floating diffusion node, a transfer gate between the sensing element and the floating diffusion node, and a charge storage device connected to the floating diffusion node via a switch. The method comprises biasing the transfer gate to three or more bias voltages OFF, ON and an intermediate bias between OFF and ON. During the period in which the transfer gate is biased to the intermediate bias, if the sensor reaches saturation, the overflown charges may be collected and part of them stored in the charge storage device, for further analysis and merging.

Abstract: A method for synchronizing multiple processing units, comprises the steps of configuring a synchronization register in a target processing unit so that its content is overwritten only by bits that are set in words written in the synchronization register; assigning a distinct bit position of the synchronization register to each processing unit; and executing a program thread in each processing unit. When the program thread of a current processing unit reaches a synchronization point, the method comprises writing in the synchronization register of the target processing unit a word in which the bit position assigned to the current processing unit is set, and suspending the program thread. When all the bits assigned to the processing units are set in the synchronization register, the suspended program threads are resumed.

Abstract: The invention relates to a method for updating a variable shared between multiple processor cores. The following steps are implemented during execution in one of the cores of a local scope atomic read-modify-write instruction (AFA), having a memory address (a1) of the shared variable as a parameter: performing operations of the atomic instruction in a cache line (L(a1)) allocated to the memory address; and locally locking the cache line (LCK) while authorizing access to the shared variable by cores connected to another cache memory of same level during execution of the local scope atomic instruction.