Abstract: A circuit includes a first processing unit and a second identical processing unit. A first communication bus passes encrypted data between one of a plurality of functions and one or both of the first and second processing units. A selection circuit determines whether the encrypted bus is coupled to the first processing unit, the second processing unit, or both of the first and second processing units.

Abstract: A circuit includes a first processing unit and a second identical processing unit. A first communication bus passes encrypted data between one of a plurality of functions and one or both of the first and second processing units. A selection circuit determines whether the encrypted bus is coupled to the first processing unit, the second processing unit, or both of the first and second processing units.

Abstract: The invention relates to a decoding device particularly adapted to decode a digital input signal (E) in a transmission system using direct sequence spread spectrum, this digital input signal (E) being composed of symbols, each symbol representing a bit satisfying a Barker code, and comprising several symbol elements. This device comprises several finite response filters (FLT1 to FLT4) each of which receives the digital input signal (E), a clock circuit (CLK_GEN) outputting clock signals (CLK1 to CLK4) to the filters with a frequency equal to the frequency at which symbol elements are produced and uniformly distributed phase shifts, and an analysis circuit (ANL) designed to identify which of the filters is best tuned to the input signal (E) and to control the clock circuit to make it generated a clock signal (CLK5) optimised for decoding and an analysis circuit.

Abstract: A receiver device for a modulated signal, suited in particular to a transmission system using a binary carrier phase modulation by means of a binary message on which a direct sequence spread spectrum operation has been carried out, this device comprising a first analog radio frequency part, transforming the signal received into a low-frequency, demodulated signal, said demodulated signal being applied to a second digital part of said device comprising an analog-to-digital converter and a filter matched to the spreading code used in order to delete the spreading applied to the original message, said device being characterized in that it includes an additional filtering unit, arranged between the analog-to-digital converter and the matched filter, said filtering unit implementing a stochastic matched filtering operation in order to improve the signal-to-noise ratio at the input of said matched filter.

Abstract: A BPSK type reception device that includes a decoder for decoding a digital input signal, first and second comparators for delivering a decoded data signal and a data capture clock signal also includes a clock generator for generating a replacement clock signal, first and second latches controlled by the replacement clock signal to store the data taken, respectively, from the decoded data signal and from a signal that represents the sign of the signal at the output of the decoder, and a selection circuit for capturing, at each pulse edge of a clock signal that is offset with respect to the replacement clock signal, either the stored data originating in the sign signal in the case of loss of the previous data capture clock pulse edge at the output of the clock comparator, or the stored data originating in the data signal.

Abstract: A device for decoding a direct sequence spread spectrum-encoded binary message includes a sampler that captures at least one sequence of binary samples corresponding to one bit of the transmitted message. The captured sequence of samples are applied to a filter matched to the spreading code used, thus making it possible to delete the spreading applied to the original message. The device further includes, at the output of the sampler, an error correction block including a memory storing a plurality of binary sequences corresponding to all of the possible values for a captured sequence of samples. A replacement circuit replaces the captured sequence of samples with the stored sequence, thereby minimizing the number of samples different from the captured sequence of samples, and allowing the stored sequence to be applied to the matched filter.

Abstract: A digital processing device is at the input of a radio frequency receiver chain, suited to a transmission system using a direct sequence spectrum spread, comprising analog-to-digital conversion means (ADC) performing an undersampling of a signal received, resulting in an overlapping of the wanted signal by the transmission channel noise, demodulation means connected to the output of the ADC, a low pass filter connected at the output of the demodulation means and a filter matched to the spreading code used, wherein the ADC includes a comparator capable of comparing the amplitude of the undersampled signal to a reference in order to carry out a quantizing of the 1-bit signal, said comparator bringing about the creation of a quantizing noise, and including an additional filtering unit arranged between the low pass filter and the matched filter, implementing a multi-noise, stochastic matched filtering operation.

Abstract: A BPSK type reception device that includes a decoder for decoding a digital input signal, first and second comparators for delivering a decoded data signal and a data capture clock signal also includes a clock generator for generating a replacement clock signal, first and second latches controlled by the replacement clock signal to store the data taken, respectively, from the decoded data signal and from a signal that represents the sign of the signal at the output of the decoder, and a selection circuit for capturing, at each pulse edge of a clock signal that is offset with respect to the replacement clock signal, either the stored data originating in the sign signal in the case of loss of the previous data capture clock pulse edge at the output of the clock comparator, or the stored data originating in the data signal.

Abstract: A digital processing device for a modulated signal, arranged at the input of a radio frequency receiver chain, suited in particular to a transmission system a direct sequence spread spectrum operation, comprising an analog-to-digital converter performing undersampling of the signal received, leading to an overlapping of the frequency range of the undersampled wanted signal by the frequency range of an interfering signal, demodulation means connected at the output of the analog-to-digital converter in order to bring the undersampled wanted signal back to baseband, a low pass filter connected at the output of the demodulation means and a filter matched to the spreading code used, and an additional filtering unit arranged between the low pass filter and the matched filter, for implementing a stochastic matched filtering operation to improve the signal-to-noise ratio at the input of the matched filter.

Abstract: A receiver device for a modulated signal, suited in particular to a transmission system using a binary carrier phase modulation by means of a binary message on which a direct sequence spread spectrum operation has been carried out, this device comprising a first analog radio frequency part, transforming the signal received into a low-frequency, demodulated signal, said demodulated signal being applied to a second digital part of said device comprising an analog-to-digital converter and a filter matched to the spreading code used in order to delete the spreading applied to the original message, said device being characterized in that it includes an additional filtering unit, arranged between the analog-to-digital converter and the matched filter, said filtering unit implementing a stochastic matched filtering operation in order to improve the signal-to-noise ratio at the input of said matched filter.

Abstract: The invention relates to a decoding device particularly adapted to decode a digital input signal (E) in a transmission system using direct sequence spread spectrum, this digital input signal (E) being composed of symbols, each symbol representing a bit satisfying a Barker code, and comprising several symbol elements. This device comprises several finite response filters (FLT1 to FLT4) each of which receives the digital input signal (E), a clock circuit (CLK_GEN) outputting clock signals (CLK1 to CLK4) to the filters with a frequency equal to the frequency at which symbol elements are produced and uniformly distributed phase shifts, and an analysis circuit (ANL) designed to identify which of the filters is best tuned to the input signal (E) and to control the clock circuit to make it generated a clock signal (CLK5) optimised for decoding and an analysis circuit.

Abstract: The present invention relates to an integrated circuit comprising a central processing unit clocked by a clock signal, a main oscillator circuit supplying a first clock signal and a peripheral circuit supplying a periodic wake up signal, the central processing unit comprising a first operating mode at full power, in which the first clock signal is applied to the central processing unit, and an active halt mode in which the main oscillator circuit and the central processing unit are deactivated, the central processing unit being awakened by the periodic wake-up signal.