Abstract: The instant disclosure relates to an electronic image detection device comprising: a plurality of metal electrodes on a first face of an insulating layer; and amorphous silicon regions extending over the insulating layer between the metal electrodes.

Abstract: A time-delay-integration image sensor comprises a matrix of pixels organized in rows and columns. Each pixel comprises a first photosensitive element, a storage node and a first transfer element connected between the first photosensitive element and the storage node, Each pixel further comprises a second photosensitive element, a second transfer element connected between the second photosensitive element and the storage node, and a third transfer element connected between the storage node and the second photosensitive element of an adjacent pixel of the column. A control circuit is configured to simultaneously command the first and second transfer elements to on state and the third transfer element to off state, and, in a distinct phase, to simultaneously command the first and third transfer elements to on state and the second transfer element to off state.

Abstract: An time-delay-integration image sensor comprises a matrix of photosensitive pixels organized in rows and columns, a first matrix of memory cells associated with control and adding means to store accumulated brightness levels of several rows of pixels in a row of memory cells. The first memory cell matrix is provided with the control and adding means to store in its rows accumulated brightness levels of the rows of a first half of the pixel matrix. The sensor comprises a second memory cell matrix associated with the control and adding means to store accumulated brightness levels of the rows of the second half of the pixel matrix in a row of the second memory cell matrix. Means are provided for adding the levels accumulated in a row of the first memory cell matrix to the levels accumulated in a corresponding row of the second memory cell matrix.

Abstract: This method for producing a non-planar microelectronic component, especially a concave component, involves superposing a layer that contains an active flexible circuit above a cavity shaped according to the desired profile of said component, said cavity being formed in substrate; and applying a pressure difference either side of said layer thereby causing slumping of the flexible circuit into the cavity therefore causing the circuit to assume the shape of the cavity. Superposition of the flexible circuit and the cavity is realized by filling the cavity with a material capable of being selectively removed relative to the substrate and the flexible circuit; then fitting or forming the flexible circuit on the cavity thus filled; then forming at least one feedthrough to access the filled cavity; and by selectively etching the material that fills the cavity via at least one feedthrough in order to remove said material.

Abstract: The invention relates to a process for manufacturing a device comprising electronic components (20a, 20b) in regions (32a, 32b) of a layer of semi conducting material (12), these regions being insulated from each other.

Abstract: A microelectronic structure with a low voltage part and high voltage part, such that the low voltage part is protected against the high voltage part and process of obtaining this protection. The structure includes at least one low-voltage element (2) and at least high-voltage element (4) formed on a semi-conductor substrate (6). According to the invention, at least one channel (18) is formed, passing through the low-voltage element and one semi-conductor zone is formed with doping opposite to that of the substrate, at least around the walls of the channel or channels and a contact point (24) is established in this zone. Application to smart power integrated circuits.

Abstract: A device for the interconnection of at least two electronic elements separated by at least one buffer zone. The interconnection includes one or more interconnection tracks for the elements, which tracks are perforated at least in parts of the track or tracks situated above the buffer zones.

Abstract: Device for the protection of an electrical load. A branch (4) connects an input terminal (1) to an output terminal (2). The branch includes in series:a channel of a first transistor (10) of the "normally on" type anda channel of a second transistor (20) of the "normally on" type of a second conductivity type. A gate (10g) of the first transistor (10) is connected to the output terminal (2) and a gate (20g) of the second transistor (20) is connected to the input terminal (1) by means of a third "normally on" transistor (30) of the first conductivity type. A gate (30g) is connected to a node (6) between the channels of the first and second transistors. The device has application to the protection of electronic components.

Abstract: Method for producing a silicon technology transistor on a nonconductor. This method consists in particular of forming a thin film of silicon (6) on a nonconductor (4) and then a mask (8, 10) including one opening (13) at the location provided for the channel (26) of the transistor; of locally oxidizing (14) the unmasked silicon to form an oxidation film; of eliminating the mask; of forming source (18) and drain (20) regions in the silicon by ion implantation with the oxidation film being used to mask this implantation; of eliminating the oxidation film; and of forming a thin gate nonconductor between the source and the drain and then forming the gate.

Abstract: A static memory cell of the metal-insulator-semiconductor type, which can be used in the microelectronics field for producing random access memories for storing binary information. This MIS type memory cell is a random access static memory cell known under the abbreviation SRAM. A bistable flip-flop is formed by a MIS transistor and a parasitic bipolar transistor. The source and drain of the MIS transistor respectively formed by constituting the emitter and collector of the bipolar transistor. The region of the channel of the MIS transistor located between the source and drain serves as the base for the bipolar transistor. The base is completely isolated from the outside of the memory cell. The gate electrode of the MIS transistor is electrically isolated from the region of the channel. There is an addressing circuit for the flip-flop for storing binary information in the form of the absence or presence of current.