Patents by Inventor Benoit J. Meister

Benoit J. Meister has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907549
    Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: February 20, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Muthu Manikandan Baskaran, Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, M. H. Langston, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Patent number: 11789769
    Abstract: In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: October 17, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Muthu M. Baskaran, Thomas Henretty, M. H. Langston, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache, David E. Wohlford
  • Patent number: 11726197
    Abstract: A system for determining the physical path of an object can map several candidate paths to a suitable path space that can be explored using a convex optimization technique. The optimization technique may take advantage of the typical sparsity of the path space and can identify a likely physical path using a function of sensor observation as constraints. A track of an object can also be determined using a track model and a convex optimization technique.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: August 15, 2023
    Assignee: QUALCOMM Technologies, Inc.
    Inventors: Muthu M. Baskaran, Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, M. H. Langston, Janice O. McMahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Patent number: 11693636
    Abstract: An approach is presented to enhancing the optimization process in a polyhedral compiler by introducing compile-time versioning, i.e., the production of several versions of optimized code under varying assumptions on its run-time parameters. We illustrate this process by enabling versioning in the polyhedral processor placement pass. We propose an efficient code generation method and validate that versioning can be useful in a polyhedral compiler by performing benchmarking on a small set of deep learning layers defined for dynamically-sized tensors.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: July 4, 2023
    Assignee: Reservoir Labs Inc.
    Inventors: Benoit J. Meister, Adithya Dattatri
  • Patent number: 11579905
    Abstract: A compilation system can define, at compile time, the data blocks to be managed by an Even Driven Task (EDT) based runtime/platform, and can also guide the runtime/platform on when to create and/or destroy the data blocks, so as to improve the performance of the runtime/platform. The compilation system can also guide, at compile time, how different tasks may access the data blocks they need in a manner that can improve performance of the tasks.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: February 14, 2023
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu Manikandan Baskaran, Benoit J. Meister, Benoit Pradelle
  • Patent number: 11573945
    Abstract: In a system for storing in memory a tensor that includes at least three modes, elements of the tensor are stored in a mode-based order for improving locality of references when the elements are accessed during an operation on the tensor. To facilitate efficient data reuse in a tensor transform that includes several iterations, on a tensor that includes at least three modes, a system performs a first iteration that includes a first operation on the tensor to obtain a first intermediate result, and the first intermediate result includes a first intermediate-tensor. The first intermediate result is stored in memory, and a second iteration is performed in which a second operation on the first intermediate result accessed from the memory is performed, so as to avoid a third operation, that would be required if the first intermediate result were not accessed from the memory.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 7, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Muthu Manikandan Baskaran, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache
  • Patent number: 11567746
    Abstract: In a sequence of major computational steps or in an iterative computation, a stencil amplifier can increase the number of data elements accessed from one or more data structures in a single major step or iteration, thereby decreasing the total number of computations and/or communication operations in the overall sequence or the iterative computation. Stencil amplification, which can be optimized according to a specified parameter such as compile time, rune time, code size, etc., can improve the performance of a computing system executing the sequence or the iterative computation in terms of run time, memory load, energy consumption, etc. The stencil amplifier typically determines boundaries, to avoid erroneously accessing data elements not present in the one or more data structures.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: January 31, 2023
    Assignee: Qualcomm Technologies Inc.
    Inventors: Muthu M. Baskaran, Thomas Henretty, Richard A. Lethin, Benoit J. Meister
  • Patent number: 11537373
    Abstract: A system for compiling programs for execution thereof using a hierarchical processing system having two or more levels of memory hierarchy can perform memory-level-specific optimizations, without exceeding a specified maximum compilation time. To this end, the compiler system employs a polyhedral model and limits the dimensions of a polyhedral program representation that is processed by the compiler at each level using a focalization operator that temporarily reduces one or more dimensions of the polyhedral representation. Semantic correctness is provided via a defocalization operator that can restore all polyhedral dimensions that had been temporarily removed.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: December 27, 2022
    Assignee: Qualcomm Technologies, Inc.
    Inventors: Muthu Manikandan Baskaran, Benoit J. Meister, Benoit Pradelle
  • Patent number: 11500557
    Abstract: A compilation system using an energy model based on a set of generic and practical hardware and software parameters is presented. The model can represent the major trends in energy consumption spanning potential hardware configurations using only parameters available at compilation time. Experimental verification indicates that the model is nimble yet sufficiently precise, allowing efficient selection of one or more parameters of a target computing system so as to minimize power/energy consumption of a program while achieving other performance related goals. A voltage and/or frequency optimization and selection is presented which can determine an efficient dynamic hardware configuration schedule at compilation time. In various embodiments, the configuration schedule is chosen based on its predicted effect on energy consumption. A concurrency throttling technique based on the energy model can exploit the power-gating features exposed by the target computing system to increase the energy efficiency of programs.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 15, 2022
    Assignee: Reservoir Labs Inc.
    Inventors: Muthu M. Baskaran, Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, M. H. Langston, Janice O. McMahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Patent number: 11500621
    Abstract: Methods, apparatus and computer software product for optimization of data transfer between two memories includes determining access to master data stored in one memory and/or to local data stored in another memory such that either or both of the size of total data transferred and the number of data transfers required to transfer the total data can be minimized. The master and/or local accesses are based on, at least in part, respective structures of the master and local data.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 15, 2022
    Assignee: Reservoir Labs Inc.
    Inventors: Richard A. Lethin, Allen K. Leung, Benoit J. Meister, David E. Wohlford
  • Patent number: 11481329
    Abstract: A technique to facilitate efficient, parallelized execution of a program using a multiprocessor system having two or more processors includes detecting and, optionally, minimizing broadcast data communication between a shared memory and two or more processors. To this end, the broadcast space of a data structure is generated as an intersection of the reuse space of the data structure and the placement space of a statement accessing the data structure. A non-empty broadcast space implies broadcast data communication that can be minimized by rescheduling the statement accessing the data structure.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: October 25, 2022
    Assignee: Reservoir Labs, Inc.
    Inventor: Benoit J. Meister
  • Publication number: 20220229641
    Abstract: An approach is presented to enhancing the optimization process in a polyhedral compiler by introducing compile-time versioning, i.e., the production of several versions of optimized code under varying assumptions on its run-time parameters. We illustrate this process by enabling versioning in the polyhedral processor placement pass. We propose an efficient code generation method and validate that versioning can be useful in a polyhedral compiler by performing benchmarking on a small set of deep learning layers defined for dynamically-sized tensors.
    Type: Application
    Filed: November 15, 2021
    Publication date: July 21, 2022
    Inventors: Benoit J. Meister, Adithya Dattatri
  • Patent number: 11372629
    Abstract: A technique for efficient scheduling of operations in a program for parallelized execution thereof using a multi-processor runtime environment having two or more processors includes constraining the type or number of loop optimization transforms that may be explored such that memory and processing capacity available for the scheduling task are not exceeded, while facilitating a tradeoff between memory locality, parallelization, and/or data communication between memory modules of the multi-processor runtime environment.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 28, 2022
    Assignee: Reservoir Labs, Inc.
    Inventors: Benoit J. Meister, Eric Papenhausen
  • Publication number: 20220114000
    Abstract: A compilation system can define, at compile time, the data blocks to be managed by an Even Driven Task (EDT) based runtime/platform, and can also guide the runtime/platform on when to create and/or destroy the data blocks, so as to improve the performance of the runtime/platform. The compilation system can also guide, at compile time, how different tasks may access the data blocks they need in a manner that can improve performance of the tasks.
    Type: Application
    Filed: October 26, 2021
    Publication date: April 14, 2022
    Inventors: Muthu Manikandan Baskaran, Benoit J. Meister, Benoit Pradelle
  • Publication number: 20220057949
    Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.
    Type: Application
    Filed: June 24, 2021
    Publication date: February 24, 2022
    Inventors: Muthu Manikandan Baskaran, Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, M. H. Langston, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Publication number: 20220004425
    Abstract: In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.
    Type: Application
    Filed: February 14, 2020
    Publication date: January 6, 2022
    Inventors: Muthu M. Baskaran, Thomas Henretty, M. H. Langston, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache, David E. Wohlford
  • Patent number: 11200035
    Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one local memory unit that allows for data reuse opportunities. The first custom computing apparatus optimizes the code for reduced communication execution on the second computing apparatus.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 14, 2021
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu M. Baskaran, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache
  • Patent number: 11188363
    Abstract: A compilation system can define, at compile time, the data blocks to be managed by an Even Driven Task (EDT) based runtime/platform, and can also guide the runtime/platform on when to create and/or destroy the data blocks, so as to improve the performance of the runtime/platform. The compilation system can also guide, at compile time, how different tasks may access the data blocks they need in a manner that can improve performance of the tasks.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: November 30, 2021
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu Manikandan Baskaran, Benoit J. Meister, Benoit Pradelle
  • Publication number: 20210255891
    Abstract: In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: Thomas Henretty, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache, David E. Wohlford
  • Publication number: 20210232379
    Abstract: A system for compiling programs for execution thereof using a hierarchical processing system having two or more levels of memory hierarchy can perform memory-level-specific optimizations, without exceeding a specified maximum compilation time. To this end, the compiler system employs a polyhedral model and limits the dimensions of a polyhedral program representation that is processed by the compiler at each level using a focalization operator that temporarily reduces one or more dimensions of the polyhedral representation. Semantic correctness is provided via a defocalization operator that can restore all polyhedral dimensions that had been temporarily removed.
    Type: Application
    Filed: September 28, 2020
    Publication date: July 29, 2021
    Inventors: Muthu Manikandan Baskaran, Benoit J. Meister, Benoit Pradelle