Patents by Inventor Benoit Lemonnier
Benoit Lemonnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10268797Abstract: Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.Type: GrantFiled: November 21, 2013Date of Patent: April 23, 2019Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8966415Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state.Type: GrantFiled: October 25, 2013Date of Patent: February 24, 2015Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8819608Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.Type: GrantFiled: July 22, 2008Date of Patent: August 26, 2014Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Publication number: 20140082579Abstract: Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform.Type: ApplicationFiled: November 21, 2013Publication date: March 20, 2014Applicant: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Publication number: 20140053120Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state.Type: ApplicationFiled: October 25, 2013Publication date: February 20, 2014Applicant: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8595674Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. According to another aspect, the present invention circuit design discloses incremental force directed placement transforms utilizing resource layers to address the heterogeneous resource distribution problem, where the force on an instance can be a weighted average of the forces from its resource layers based on the local congestion of those resources.Type: GrantFiled: July 22, 2008Date of Patent: November 26, 2013Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Patent number: 8589850Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.Type: GrantFiled: July 22, 2008Date of Patent: November 19, 2013Assignee: Synopsys, Inc.Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Publication number: 20090031278Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. According to another aspect, the present invention circuit design discloses incremental force directed placement transforms utilizing resource layers to address the heterogeneous resource distribution problem, where the force on an instance can be a weighted average of the forces from its resource layers based on the local congestion of those resources.Type: ApplicationFiled: July 22, 2008Publication date: January 29, 2009Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin
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Publication number: 20090031277Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.Type: ApplicationFiled: July 22, 2008Publication date: January 29, 2009Inventors: Kenneth S. McElvain, Benoit Lemonnier, William Halpin