Abstract: A method of implementing a circuit design for a target device can include assigning load pins of a high fanout signal of a placed circuit design into a plurality of windows according to a location of each load pin on the target device. A source of the high fanout signal can be replicated, wherein each window is associated with a source of the high fanout signal. For each source of the high fanout signal, the source can be connected to load pins of the window associated with the source and the source can be placed within the window associated with the source. The placed circuit design can be output.

Abstract: A reconfigurable module in a programmable logic device (“PLD”), such as a field-programmable gate array (“FPGA”), is reset after reconfiguration by an internal reset signal. The internal reset signal allows other modules in the PLD to remain active while the reconfigurable module is reconfigured and reset. The internal reset signal is generated by a reset manager circuit that optionally resides within the reconfigurable module.