Patents by Inventor Benoit Sklenard

Benoit Sklenard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985317
    Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 20, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Marios Barlas, Philippe Blaise, Laurent Grenouillet, Benoît Sklenard, Elisa Vianello
  • Publication number: 20200127199
    Abstract: A device for selecting a storage cell, includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, wherein the oxide layer is doped with a first element from column IV of the periodic table.
    Type: Application
    Filed: September 8, 2017
    Publication date: April 23, 2020
    Inventors: Mario BARLAS, Philippe BLAISE, Laurent GRENOUILLET, Benoît SKLENARD, Elisa VIANELLO
  • Publication number: 20190280203
    Abstract: A resistive non-volatile memory cell includes a first electrode, a second electrode and an oxide layer disposed between the first electrode and the second electrode, the memory cell being capable of reversibly switching between: —a high resistance state obtained by applying a first bias voltage between the first electrode and the second electrode; and—a low resistance state obtained by applying a second bias voltage between the first electrode and the second electrode; the oxide layer including a switching zone forming a conduction path prioritised for the current passing through the memory cell when the memory cell is in the low resistance state. The oxide layer includes a first zone doped with aluminium or silicon, the aluminium or silicon being present in the first zone with an atomic concentration that is selected so as to locate the switching zone outside the first zone.
    Type: Application
    Filed: September 8, 2017
    Publication date: September 12, 2019
    Inventors: Laurent GRENOUILLET, Marios BARLAS, Philippe BLAISE, Benoît SKLENARD, Elisa VIANELLO
  • Patent number: 9966453
    Abstract: Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer (16) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer (16) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Shay Reboh, Perrine Batude, Frederic Mazen, Benoit Sklenard
  • Publication number: 20160300927
    Abstract: Method including the steps consisting in: forming source and drain semiconductor blocks comprising a first layer based on a first crystalline semiconductor material surmounted by a second layer (16) based on a second crystalline semiconductor material different from the first semiconductor material, making amorphous and selectively doping the second layer (16) by means of one or more implantation(s), carrying out a recrystallisation of the second layer and an activation of dopants by means of at least one thermal annealing.
    Type: Application
    Filed: April 6, 2016
    Publication date: October 13, 2016
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Shay REBOH, Perrine BATUDE, Frederic MAZEN, Benoit SKLENARD
  • Patent number: 9379213
    Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 28, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS SA
    Inventors: Perrine Batude, Jean-Michel Hartmann, Benoit Sklenard, Maud Vinet
  • Patent number: 9343375
    Abstract: Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphization of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphization of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallization of the source and drain blocks such that the second semiconducting material i
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: May 17, 2016
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Perrine Batude, Frederic Mazen, Shay Reboh, Benoit Sklenard
  • Patent number: 9246006
    Abstract: A method for manufacturing a transistor is provided, including amorphization and doping, by one or more localized implantations, of given regions of source and drain blocks based on crystalline semi-conductor material disposed on an insulating layer of a semi-conductor on insulator substrate, the implantations being carried out so as to conserve at a surface of said blocks zones of crystalline semi-conductor material on regions of amorphous semi-conductor material; and recrystallization of at least one portion of said given regions.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: January 26, 2016
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMICROELECTRONICS SA
    Inventors: Perrine Batude, Frederic Mazen, Benoit Sklenard, Shay Reboh
  • Publication number: 20160020153
    Abstract: Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps: epitaxial growth of zones made of a second semiconducting material on the layer made of a first crystalline semiconducting material, so as to form source and drain blocks with the layer made of a first crystalline semiconducting material on each side of the channel, the second semiconducting material having a lattice parameter different from that of the first semiconducting material, in-depth amorphisation of part of zones made of a second semiconducting material so as to keep only one layer of second crystalline semiconducting material on the surface of the source and drain blocks, and amorphisation of zones of the layer made of a first semiconducting material located under zones made of a second semiconducting material, recrystallisation of the source and drain blocks such that the second semiconducting material i
    Type: Application
    Filed: July 17, 2015
    Publication date: January 21, 2016
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Perrine BATUDE, Frederic MAZEN, Shay REBOH, Benoit SKLENARD
  • Patent number: 9018078
    Abstract: A method for manufacturing an integrated circuit, including the steps of forming first transistors on a first semiconductor layer; depositing a first insulating layer above the first semiconductor layer and the first transistors, and leveling the first insulating layer; depositing a conductive layer above the first insulating layer, and covering the conductive layer with a second insulating layer; bonding a semiconductor wafer to the second insulating layer; thinning the semiconductor wafer to obtain a second semiconductor layer; and forming second transistors on the second semiconductor layer.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics SA, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Benoit Sklenard, Perrine Batude
  • Publication number: 20150044841
    Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 12, 2015
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS SA
    Inventors: Perrine BATUDE, Jean-Michel HARTMANN, Benoit SKLENARD, Maud VINET
  • Publication number: 20150044828
    Abstract: A Method for manufacturing a transistor comprising: a) amorphization and doping, by means of one or more localised implantation(s), of given regions of source and drain blocks based on crystalline semi-conductor material lying on an insulating layer of a semi-conductor on insulator substrate, the implantation(s) being carried out so as to conserve at the surface of said blocks zones of crystalline semi-conductor material on the regions of amorphous semi-conductor material, b) recrystallization of at least one portion of said given regions.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 12, 2015
    Applicants: COMMISARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS SA
    Inventors: Perrine BATUDE, Frederic Mazen, Benoit Sklenard