Patents by Inventor Benson Liu

Benson Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9601443
    Abstract: A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
    Type: Grant
    Filed: February 13, 2007
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Shih-Hsun Hsu, Shih-Cheng Chang, Shang-Yun Hou, Hsien-Wei Chen, Chia-Lun Tsai, Benson Liu, Shin-Puu Jeng, Anbiarshy Wu
  • Patent number: 8618673
    Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 31, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Benson Liu, Hsien-Wei Chen, Shin-Puu Jeng, Hao-Yi Tsai
  • Publication number: 20120267799
    Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Benson LIU, Hsien-Wei CHEN, Shin-Puu JENG, Hao-Yi TSAI
  • Patent number: 8237253
    Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: August 7, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Benson Liu, Hsien-Wei Chen, Shin-Puu Jeng, Hao-Yi Tsai
  • Patent number: 8227917
    Abstract: A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: July 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hsun Hsu, Hao-Yi Tsai, Benson Liu, Chia-Lun Tsai, Hsien-Wei Chen, Anbiarshy N. F. Wu, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20110062597
    Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
    Type: Application
    Filed: November 16, 2010
    Publication date: March 17, 2011
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Benson LIU, Hsien-Wei Chen, Shin-Puu Jeng, Hao-Yi Tsai
  • Patent number: 7859092
    Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
    Type: Grant
    Filed: January 2, 2007
    Date of Patent: December 28, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Benson Liu, Hsien-Wei Chen, Shin-Puu Jeng, Hao-Yi Tsai
  • Publication number: 20090091032
    Abstract: A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.
    Type: Application
    Filed: October 8, 2007
    Publication date: April 9, 2009
    Inventors: Shih-Hsun Hsu, Hao-Yi Tsai, Benson Liu, Chia-Lun Tsai, Hsien-Wei Chen, Anbiarshy N.F. Wu, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20090081862
    Abstract: A method for forming air gaps between interconnect structures in semiconductor devices provides a sacrificial layer formed over a dielectric and within openings formed therein. The sacrificial layer is a blanket layer that is converted to a material that is consumable in an etchant composition that the dielectric material and a subsequently formed interconnect material are resistant to. After the interconnect material is deposited a planarized surface including portions of the dielectric material, vertical sections of the converted material and portions of the interconnect material is produced. The etchant composition then removes the converted material thereby forming voids. A capping layer is formed over the structure resulting in air gaps. A sidewall protection layer may be optionally formed between the interconnect structure and the sacrificial material. In some embodiments an ARC layer may be formed over the dielectric and form part of the planar surface.
    Type: Application
    Filed: September 24, 2007
    Publication date: March 26, 2009
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Benson Liu
  • Publication number: 20080246031
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe line and exposed on the surface of the scribe lines, wherein the conductive feature has an edge facing the semiconductor chip. A kerf path is in the scribe line. A first cut is formed in the conductive feature, wherein the first cut extends from the first edge to the kerf path.
    Type: Application
    Filed: April 9, 2007
    Publication date: October 9, 2008
    Inventors: Hao-Yi Tsai, Shih-Hsun Hsu, Hsien-Wei Chen, Benson Liu, Chia-Lun Tsai, Anbiarshy N.F. Wu
  • Publication number: 20080191205
    Abstract: A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
    Type: Application
    Filed: February 13, 2007
    Publication date: August 14, 2008
    Inventors: Hao-Yi Tsai, Shih-Hsun Hsu, Shih-Cheng Chang, Shang-Yun Hou, Hsien-Wei Chen, Chia-Lun Tsai, Benson Liu, Shin-Puu Jeng, Anbiarshy Wu
  • Publication number: 20080157315
    Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.
    Type: Application
    Filed: January 2, 2007
    Publication date: July 3, 2008
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Benson Liu, Hsien-Wei Chen, Shin-Puu Jeng, Hao-Yi Tsai