Abstract: Various embodiments may provide a transistor. The transistor may include a substrate, a first contact electrode and a second contact electrode over the substrate. The transistor may additionally include a two-dimensional semiconductor material layer above the substrate such that the first contact electrode is in contact with a first portion and the second contact electrode is in contact with a second portion of the two-dimensional semiconductor material layer. The transistor may further include a first control gate and a second control gate. The transistor may additionally include a main gate over a third portion of the two-dimensional semiconductor material layer, the third portion between the first portion and the second portion. The transistor may also include a dielectric layer separating the main gate, the first control gate and the second control gate from the two-dimensional semiconductor material layer.

Abstract: This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.

Abstract: This invention concerns the fabrication of nano to atomic scale devices, that is electronic devices fabricated down to atomic accuracy. The fabrication process uses either an SEM or a STM tip to pattern regions on a semiconductor substrate. Then, forming electrically active parts of the device at those regions. Encapsulating the formed device. Using a SEM or optical microscope to align locations for electrically conducting elements on the surface of the encapsulating semiconductor with respective active parts of the device encapsulated below the surface. Forming electrically conducting elements on the surface at the aligned locations. And, electrically connecting electrically conducting elements on the surface with aligned parts of the device encapsulated below the surface to allow electrical connectivity and tunability of the device. In further aspects the invention concerns the devices themselves.