Patents by Inventor Benwei Xu

Benwei Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pipelined SAR ADC using comparator as a voltage-to-time converter with multi-bit second stage
    Patent number: 10061272
    Abstract: A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 28, 2018
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Yun Chiu, Benwei Xu
  • Pipelined SAR ADC Using Comparator As A Voltage-To-Time Converter With Multi-Bit Second Stage
    Publication number: 20170357219
    Abstract: A two-stage successive-approximation-register (SAR) analog-to-digital converter (ADC) comprising is described. The SAR ADC includes a first stage comprising a SAR ADC; a voltage-to-time interface that translates a voltage-domain residue from the SAR ADC to a time-domain residue; and a second stage comprising a time-to-digital converter (TDC) that resolves multiple bits from the time-domain residue.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 14, 2017
    Inventors: Yun CHIU, Benwei XU
  • System and method for dynamic path-mismatch equalization in time-interleaved ADC
    Patent number: 9287889
    Abstract: Disclosed are methods and systems implementing digital background calibration techniques for identifying and remedying dynamic path-mismatch errors in time-interleaved analog-to-digital converters (TI-ADC). The disclosed systems and methods employ a calibration technique specifically focuses on removing the timing skew and input bandwidth mismatches by equalizing each sub-ADC in an array to a common reference ADC using direct input derivative information. The errors are identified by correlating the ensuing conversion error to the input derivatives of various orders to identify the mismatch parameters. Simple passive high-pass filters (HPF) are used to extract input derivatives followed by one-bit quantizers.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 15, 2016
    Assignee: The Board of Regents, The University of Texas System
    Inventors: Yun Chiu, Benwei Xu
  • SYSTEM AND METHOD FOR DYNAMIC PATH-MISMATCH EQUALIZATION IN TIME-INTERLEAVED ADC
    Publication number: 20150303934
    Abstract: Disclosed are methods and systems implementing digital background calibration techniques for identifying and remedying dynamic path-mismatch errors in time-interleaved analog-to-digital converters (TI-ADC). The disclosed systems and methods employ a calibration technique specifically focuses on removing the timing skew and input bandwidth mismatches by equalizing each sub-ADC in an array to a common reference ADC using direct input derivative information. The errors are identified by correlating the ensuing conversion error to the input derivatives of various orders to identify the mismatch parameters. Simple passive high-pass filters (HPF) are used to extract input derivatives followed by one-bit quantizers.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Applicant: The Board of Regents, The University of Texas System
    Inventors: Yun Chiu, Benwei Xu